RISC-V International
| Tiejun Chen | Ozgur Ozkurt | David Weaver |
|---|---|---|
Bio Tiejun Chen is senior technical lead from Advanced Technology Group, VMware OCTO. Before joined VMware, he worked at Wind River System and Intel OTC. He's been working on a lot of areas - virtualization technologies, edge computing, ML/AI, RISC-V, WebAssembly, Linux, SmartNIC/DPU, etc. He actively contributes to open-source communities, and shared at kubecon China 2021, Kube Edge day Europe 2022, LC3 China 2017 & 2018, OSS China 2019, OSS North America 2017 & 2018, OSS & ELC Europe 2017 & 2018 & 2019, RT-Summit Europe 2017 & 2018, and ELC & OpenIoT 2018, FOSSASIA Opentech Singapore 2018, OSS & AGL Japan 2018, OSLS 2019 and also hosted some open workshops, LF Edge mini-summit, IoT meetup sponsored by Linux Foundation and or ACM. | Bio Ozgur Ozkurt is Senior Director of Engineering of CPU at Imagination Technologies. He is responsible for all RISC-V processors development across Imagination IP portfolio and joined in October 2021. Previously he managed the R-Class CPU engineering team (focused on functional safety solutions) at Arm and has held various management and technical leadership roles on Display and image signal processors since 2013. At Arm, he was a member of the Design Steering Committee across all Arm Engineering, ensuring consistency in quality and PPA analysis across product lines. Before Arm, he was a research engineer on 3D TV Solutions and Gesture Recognition at Vestek R&D Istanbul and BAU for 5 years. He has been an active member of the VESA and HDMI Consortiums. He earned his MSc in EE on Embedded Video systems in 2012 from BAU Istanbul. | Bio My career began in development of cross-development tools for embedded processors. Then, as ISA Architect for another UCB RISC-derived architecture (SPARC), I was responsible for the architectural consistency, architecture specifications, opcode space management, and coordination of all ISA extensions for 20+ yrs. That work required collaboration across many technical disciplines and across many companies. I also served for 7 years as a Director on the Board of SPARC International (an organization parallel to RISC-V International). After that, I spent a few years in Architecture Research at Arm. I currently serve as a Principal Architect at Akeana in San Jose. |
Statement of Intent Would love to help drive and accelerate the adoption of RISC-V software ecosystem from cloud to edge. Especially, as I see RISC-V has gotten noticed in many areas, but with lacking the power efforts on a key part of edge computing featured with edge native by bringing cloud native principle to edge. There are some challenges for putting RISC-V to the edge very well – | Statement of Intent Throughout my career, I have worked on holistic solutions incorporating application-specific processors, some of which are tightly integrated with CPUs. For example, I have developed gesture recognition systems utilizing multi-core processor SW combined with hardware accelerators at Vestek R&D, Image Signal Processors with embedded microcontrollers at Apical (part of Arm), and contributed to multimedia solutions at Arm consisting of CPUs, GPUs, Display, and Video processors. More recently, I have worked on CPUs with various levels of functional safety requirements. In all these projects, consistent quality assessment (QA) and consistent system architecture solutions were crucial for the success. This consistency is especially important in Functional Safety (FuSa) applications. In addition, the open-source nature of RISC-V specifications and our robust community provide an excellent opportunity to create a new consistent QA model and to create system architecture solutions across RISC-V partners. This definition will be vital for the success of some ecosystems (like Automotive SIG). I would especially like to lead activities toward creating a standard Errata Management for the specifications. I believe my involvement in TSC will allow me to elevate to the Automotive and Functional Safety SIGs progress, alongside with focus on Q&A management across RISC-V ecosystem. | Statement of Intent Given experience spanning from deeply embedded processors to high-end enterprise processors, I’m motivated to minimize fragmentation in the RISC-V architecture and see the architecture cleanly span a very wide range of implementations. That requires deliberate planning and careful choices about tradeoffs. It’s key that we maintain architectural consistency (both across contemporary implementations and over time). In order to be competitive across the full spectrum of applications, we need to round out the architecture with additional features (including many already in development in our TG’s). My experience in both the software and architecture arenas can inform TSC discussions and decisions, to help ensure that RISC-V is a robust, competitive, and long-term architecture. |
Overview
Content Tools