This page contains the single list of of all ratified technical publications.
|Specification name||Version||Publish Date||RISC-V Community||Source Repository|
|The RISC-V Instruction Set Manual|
Volume I: Unprivileged ISA
|20191213||Dec. 2019||Unprivileged Horizontal Committee||riscv/riscv-isa-manual|
|The RISC-V Instruction Set Manual|
Volume II: Privileged Architecture
|20211203||Dec. 2021||Privileged Horizontal Committee||riscv/riscv-isa-manual|
Note: Recently ratified extensions, but yet included in the full specifications above, can be found on the RISC-V Recently Ratified Extensions page.
|Specification name||Version||Publish Date||Description||RISC-V Community||Source Repository|
|Efficient Trace for RISC-V||2.0||June 2022||Specifies the signals between the RISC-V core and the encoder, compressed branch trace algorithm, and the packet format used to encapsulate the compressed branch trace information to implement processor tracing.||SOC Infrastructure Horizontal Committee||riscv-non-isa/tech-trace-spec|
|RISC-V ABIs Specification||1.0||November 2022||Provides the processor-specific application binary interface document for RISC-V||Application & Tools Horizontal Committee||riscv-non-isa/riscv-elf-psabi-doc|
|RISC-V External Debug Support||0.13.2||March 2019||Outlines a standard architecture for external debug support on RISC-V platforms.||SOC Infrastructure Horizontal Committee||riscv/tech-debug-spec|
|RISC-V Platform-Level Interrupt Controller Specification||1.0.0||February 2023||Delineates the operational parameters for a platform-level interrupt controller on RISC-V.||Privileged Software Horizontal Committee||riscv/riscv-plic-spec|
|RISC-V Supervisor Binary Interface Specification||1.0.0||May 2022||Describes the RISC-V Supervisor Binary Interface, known from here on as SBI which enables supervisor-mode (S-mode or VS-mode) software to be portable across all RISC-V implementations by defining an abstraction for platform (or hypervisor) specific functionality.||Privileged Software Horizontal Committee||riscv-non-isa/riscv-sbi-doc|
|RISC-V UEFI Protocol Specification||1.0.0||May 2022||Details all new UEFI protocols required only for RISC-V platforms.||Privileged Software Horizontal Committee||riscv-non-isa/riscv-uefi|
Note: If you do not see a specification in the above table, visit the RISC-V GitHub riscv-non-isa organization to see a complete list of all specifications which have been developed or are presently under development.
The RISC-V Architectural Compatibility Test Framework Version 3 (RISCOF version 1.X) is now available.
This framework compares two arbitrary models against each other using a reference signature (one of which should be a reference model) and automatically selects tests according to the model configuration. Because the RISC-V ISA specification allows many architectural implementation choices, a tool (RISCV-CONFIG) has been created to describe implementation configurations. The RISCOF Framework uses RISCV-CONFIG to select and configure tests.
The current test coverage includes RV[32|64]IMCFD_Zb*_zK*_Zmmul_Zicsr_Zifencei (where * means a lot of sub extensions). Work continues to expand extensions supported and configurations covered.
More information can be found in the following locations
Thanks, Allen Baum
I've made updates. When you have a moment, please review and let me know what additional changes you'd recommend.
We should add the test format spec to the list of non-ISA specs, though it is undergoing revision:
The current test suite is RV[32|64]IMCFD_Zb*_zK*_Zmmul_Zicsr_Zifencei (where * means a lot of sub extensions)
F and D may be incomplete, M is missing some coverage, Zicsr is missing a lot of coverage
Ok, I've updated the current "coverage" statement but left the statements about completeness off as those details belong in the GitHub resource, not on this page. I'll also note that "coverage" does not imply nor state completeness.