A general overview and status of various extension which are presently under development can be be found at the Specification Status page.

If you are looking for documentation on a recently ratified extension that has not yet been merged into the published specifications listed at the RISC-V Specifications page, check the table below.  Extensions with hyperlinks reflect specifications which are completely ratified by RISC-V but have not yet been merged into the final specifications.  Extensions without links can be found in the published RISC-V ISA specifications on the RISC-V Specifications page.

Specification nameRatification dateNew extension(s) or Profile(s)
RISC-V Supervisor Counter DelegationMarch 2024Smcdeleg, Ssccfg
May-Be-OperationsMarch 2024Zimop, Zcmop
RISC-V Indirect CSR Access (Smcsrind/Sscsrind)February 2024Smcsrind, Sscsrind
RISC-V Integer Conditional (Zicond) operations extensionNovember 2023Zicond
Hardware Updating of PTE A/D Bits (Svadu)November 2023Svadu
RISC-V Cycle and Instret Privilege Mode Filtering (Smcntrpmf)November 2023Smcntrpmf
Atomic Compare-and-Swap (CAS) Instructions (Zacas)November 2023Zacas
RISC-V Cryptography Extensions Volume II: Vector InstructionsSeptember 2023Zvbb, Zvbc, Zvkb, Zvkg, Zvkn, Zvknc, Zvkned, Zvkng, Zvknha, Zvknhb, Zvks, Zvksc, Zvksed, Zvksg, Zvksh, Zvkt
"Zfa" Standard Extension for Additional Floating-Point InstructionsSeptember 2023Zfa
RISC-V Advanced Interrupt ArchitectureJune 2023Smaia, Ssaia
“Zvfh/Zvfhmin:” Vector Extension for Half-Precision Floating-Point Arithmetic/Vector Extension for Minimal Half-
Precision Floating-Point Arithmetic
June 2023Zvfh, Zvfhmin
“Zihintntl” Non-Temporal Locality HintsMay 2023Zihintntl
RISC-V Code Size ReductionApril 2023Zca, Zcb, Zcd, Zce, Zcf, Zcmp, Zcmt
RISC-V ProfilesMarch 2023RVA20, RVI20, RVA22
"Zicntr" and "Zihpm" CountersMarch 2023Zicntr, Zihpm
RV32E and RV64E Base Integer Instruction SetsJanuary 2023RV32E/RV64E
“Ztso” Standard Extension for Total Store OrderingJanuary 2023Ztso
RISC-V Wait-on-Reservation-Set (Zawrs) extensionNovember 2022Zawrs
Zmmul ExtensionJune 2022Zmmul
PMP Enhancements for memory access and execution prevention on Machine mode (Smepmp)November 2021Smepmp
RISC-V Base Cache Management Operation ISA ExtensionsNovember 2021Zicbom, Zicbop, Zicboz
RISC-V Bit-Manipulation ISA-extensionsNovember 2021Zba, Zbb, Zbc, Zbs
RISC-V Count Overflow and Mode-Based Filtering ExtensionNovember 2021Sscofpmf
RISC-V Cryptography Extensions Volume I: Scalar & Entropy Source InstructionsNovember 2021Zbkb, Zbkc, Zbkx, Zknd, Zkne, Zknh, Zksed, Zksh, Zkn, Zks, Zkt, Zk, Zkr
RISC-V State Enable ExtensionNovember 2021Smstateen
RISC-V "stimecmp / vstimecmp" ExtensionNovember 2021Sstc
RISC-V Vector ExtensionNovember 2021Zve32x, Zve32f, Zve64x, Zve64f, Zve64d, Zve, Zvl32b, Zvl64b, Zvl128b, Zvl256b, Zvl512b, Zvl1024b, Zvl, Zv
The RISC-V Instruction Set Manual Volume II: Privileged Architecture November 2021

Sm1p12, Ss1p12, Sv57, Hypervisor, Svinval, Svnapot, Svpbmt

"Zfh" and "Zfhmin" Standard Extensions for Half-Precision Floating-PointNovember 2021Zfh, Zfhmin
"Zfinx", "Zdinx", "Zhinx", "Zhinxmin": Standard Extensions for Floating-Point in Integer RegistersNovember 2021Zfinx, Zdinx, Zhinx, Zhinxmin
“Zihintpause” Pause HintFebruary 2021Zihintpause
The RISC-V Instruction Set Manual Volume I: Unprivileged ISADecember 2019A, D, F, RV32I, RV64I, Zaamo, Zalrsc, Zicsr, Zifencei
The RISC-V Instruction Set Manual Volume II: Privileged Architecture December 2019C, M, Q, Sm1p11, Ss1p11, Sv32, Sv39, Sv48
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