RISC-V International
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Extension / feature | Ratified? | Spike | Qemu | Binutils | GCC | glibc | newlib | LLVM | OpenSBI | Linux | GDB |
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RV32I v2.1 | y | mainline | mainline | mainline | mainline | mainline | mainline | mainline | mainline | mainline | |
RV64I v2.1 | y | mainline | mainline | mainline | mainline | mainline | mainline | mainline | mainline | mainline | |
Big-endian support | y | mainline | mainline | ||||||||
RV32E v1.9 | n | mainline | not supported | not supported | |||||||
M (Multiplication and Division) v2.0 | y | mainline | mainline | mainline | mainline | n/a | n/a | mainline | n/a | n/a | |
A (Atomic) v2.1 | y | mainline | mainline | mainline | mainline | n/a | n/a | mainline | mainline (atomics) | mainline (atomics) | |
F (SP float) v2.2 | y | mainline | mainline | ||||||||
D (DP float) v2.2 | y | mainline | mainline | ||||||||
RVWMO v2.0 | y | mainline (emulation is seq. consistent) | mainline (emulation is seq. consistent) | n/a | n/a | n/a | n/a | n/a | mainline (barriers and locks) | mainline (barriers and locks), but needs optimization | |
ABIs (ILP32, ILP32E, ILP32F, ILP32D, LP64, LP64f, LP64D, LP64Q) | Documented ABIs | ilp32, ilp32d, lp64, lp64d | ilp32, ilp32d, lp64, lp64d | ilp32, ilp32d, lp64, lp64d | ilp32, ilp32d, lp64, lp64d | n/a | n/a | ||||
C (compressed) v2.0 | y | mainline | mainline | mainline | mainline | n/a | n/a | mainline | |||
Q (QP float) v2.2 | y | ||||||||||
Zifencei v2.0 | y | mainline | mainline | mainline | mainline | ||||||
Zihintpause v1.0 | |||||||||||
Zicsr v2.0 | y | mainline | mainline | mainline | mainline | ||||||
Counters v2.0 | n | mainline | mainline | n/a | n/a | n/a | mainline | mainline | |||
Machine ISA v1.11 (CSRs, ECALL, EBREAK, MRET/SRET/URET, WFI, Reset, NMIs, PMAs, PMP) | y | mainline | mainline | n/a | |||||||
Supervisor ISA v1.11 (CSRs, SFENCE.VMA, Sv32/Sv39/Sv48) | y | mainline | mainline | n/a | |||||||
B (bitmanip) v0.92 (Zba, Zbb, Zbc, Zbk, Zbs) | n | PR | |||||||||
K (scalar crypto) | n | PR | PR | ||||||||
P (SIMD) v0.9.4 | n | mainline (but v0.9.2!) | PR | PR | |||||||
V (vector) v0.10, Vector Extension Intrinsics, Vector Calling Convention | n | mainline | mainline (but v0.7.1) | mainline (Zvlsseg API not settled, FP16 ABI not settled) | |||||||
Ztso v0.1 | n | ||||||||||
Zam v0.1 | n | ||||||||||
H (hypervisor) v0.6.1 | |||||||||||
Zmmul v0.1 (subset of M) | |||||||||||
J (JIT/Java) | |||||||||||
TEE | |||||||||||
Snavpot | n | ||||||||||
Zfinx | n | staging branch | staging branch | staging branch | staging-branch | PR | |||||
Z*inx (with new ABIs: ILP32X/ILP64X) | PLCT | PLCT | |||||||||
SV57 | |||||||||||
Zce | PLCT | PLCT |
mainline...SW support has been merged into the main development branch of the corresponding SW project
staging branch...SW support lives in a staging branch and is not mainlined
PR...SW support exists in form of a pull request for mainline (in-review or waiting for ratification)
n/a...not applicable, not relevant, or not required
missing...currently no known implementation
empty cells...unknown status (feel free to share your knowledge)
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