Page History

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• Latest Draft Fast Interrupt Specification (v0.9-draft-20210525)20210622)
  • reverted text describing CLIC memory mapped privilege regions and added clarification text.
  • clarified 32-bit writes to clicint registers are legal but effects are not defined.
  • clarified that MPRV and SUM are obeyed on vector table accesses
• What's next:
  • 36 31 outstanding issues to be addressed.  (previously 3536).

Encoding/OpCode consistency review

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• What's next: when outstanding issues are reduced, start planning for review
• tech-chairs@lists.riscv.org - when spec is solid but not a final spec - primarily want to nail down opcode/CSR assignment and have a solid draft spec (but not a final spec ready for official Arch Review)
• Also, to remind people of what gets reviewed (as is appropriate for a given extension), see the following list.  In addition to the extension spec, please submit information about the PoCs and about utility/efficiency (although we don't need all the gory detail - a paragraph or so for each can be fine).  For items considered to not be consequential, a sentence or so explaining why should suffice.
  • Consistency with the RISC-V architecture and philosophy
  • Documentation clarity and completeness
  • Including proper distinction between normative and non-normative text
  • Motivation and rationale for the features, instructions, and CSRs
  • Utility and efficiency (relative to existing architectural features and mechanisms)
  • Is there enough value or benefit to justify the cost of implementation
  • Is the cost in terms of area, timing, and complexity reasonable
  • Proof of Concept (PoC)
  • Software PoC to ensure feature completeness and appropriateness for intended use cases
  • Hardware PoC to demonstrate reasonable implementability
  • Inappropriate references to protected IP (i.e. covered by patents, copyright, etc.)

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