Page History

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• Current Charter at https://github.com/riscv/groups/tree/main/Fast-Interrupts 
• Calendar: https://calendar.google.com/calendar/u/0/embed?src=tech.meetings@riscv.org
• Develop a low-latency, vectored, priority-based, preemptive interrupt scheme for interrupts directed to a single hart, compatible with the existing RISC-V standards. Provide both hardware specifications and software ABIs/APIs. Standardize compiler conventions for annotating interrupt handler functions.

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• Latest Draft Fast Interrupt Specification (v0.9-draft-20211012)20211109)
  • 11/09/2021 issue #48 - indicate when edge-triggered interrupts are cleared
  • 11/09/2021 issue #179 - set interrupt bit during nxti access
  • updated mandatory reset requirements - removed nlbits, nmbits, clicintattr.mode reset requirements
• What's next:
  • 28 23 outstanding issues to be addressed.  

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