Page History

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• Current Charter at https://github.com/riscv/groups/tree/main/Fast-Interrupts 
• Calendar: https://calendar.google.com/calendar/u/0/embed?src=tech.meetings@riscv.org
• Develop a low-latency, vectored, priority-based, preemptive interrupt scheme for interrupts directed to a single hart, compatible with the existing RISC-V standards. Provide both hardware specifications and software ABIs/APIs. Standardize compiler conventions for annotating interrupt handler functions.
• Meetings Disclaimers Video

Specification

• Latest Draft Fast Interrupt Specification (v0.9-draft-20220104)
  • 01/04/2022 issue #45 - remove new alignment constraint on CLINT mode when CLIC added
  • 01/04/2022 issue #188 - clarification that writes to xcause affect xstatus
• What's next:
  • 23 outstanding issues. 
    • 10 active spec issues.
      • 1 issue (new CSR address) dependent on opcode review
    • 5 issues to track Definition of Done tasks
    • 7 issues kept open for future enhancements (post rev1.0)  

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