Page History

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Develop final charter and plan with the group and send to Chairs (tech-chairs@lists.riscv.org) for approval within 4 weeks
Fill in DoD Plan tab in checklist and send to chairs for approval of any deliverables that don't match the defaults along with any requested waivers
Freeze-time preliminary POC definition approved by IC
Fill in task group and specification status spreadsheet information including extension or extension group names, projected dates, DoD component effort sizing, DoD tasks your group needs resource help with,...
Develop Rationale document and send to chairs for approval
Notify TSC and Chairs when you complete this milestone and include any waivers and an updated DoD spreadsheet.

Charter

Current Charter at https://github.com/riscv/groups/tree/main/Fast-Interrupts to be moved to https://github.com/riscv-admin-docs (possibly renamed)
Develop a low-latency, vectored, priority-based, preemptive interrupt scheme for interrupts directed to a single hart, compatible with the existing RISC-V standards. Provide both hardware specifications and software ABIs/APIs. Standardize compiler conventions for annotating interrupt handler functions.

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Deterministic Test plan for the fast-interrupt is available. Discussion on-going on how to add async/undeterministic testing of interrupts.
YAML config needs to be created. See info here.
Discussion in Arch tests group to add automation (docker?) to validate check-in so that arch-test-suite is run against sail, spike, gcc/toolchain, with versions used recorded. So sail and spike will need to work for CLIC before CLIC tests can be added to riscv-config github.

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