This page gives an overview of the extension and feature support in the RISC-V SW ecosystem.
Overview
- This page only tracks extensions and features that are specified by groups (TGs, HCs) of RISC-V International.
- The extensions and features are grouped by their specification's state.
- Published (official) specifications can be found here: https://riscv.org/technical/specifications/
- The main repository of the ISA specifications is: https://github.com/riscv/riscv-isa-manual
- The On Deck Dashboards lists the specifications that are frozen and ready for ratification
Table description
The subsections below contain tables that summarize the current state of extensions and features. The following description helps to interpret the table cell's contents:
- upstream...SW support has been merged into the main development branch of the corresponding SW project
- staging branch...SW support lives in a staging branch and is not upstreamed
- PR...SW support exists in form of a pull request for upstream (in-review or waiting for ratification)
- n/a...not applicable, not relevant, or not required
- missing...currently no known implementation
- dev:X...feature is in development by X
- empty cells...unknown status (feel free to share your knowledge)
Published specifications (20191213)
...
Unpublished ratified extensions
Extension | Spike | Qemu | Binutils | GCC | glibc | newlib | LLVM | OpenSBI | FreeBSD | Linux | GDB |
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Zihintpause |
|
| upstream |
|
|
| not supported |
|
|
|
|
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Specifications that are at least frozen
...