RISC-V International
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Note: Recently ratified extensions, but yet included in the full specifications above, can be found on the RISC-V Recently Ratified Extensions page.
Compatibility Test Framework
The RISC-V Architectural Compatibility Test Framework Version 2 is now available. This framework compares arbitrary models against a reference signature, and currently covers RV[32|64]IMC unprivileged specifications only. Tests for the not-yet-ratified Crypto Scalar extension and RV32EMC extensions are also available.
Work on Version 3.0 framework (RISCOF) is underway which will compare two arbitrary models against each other (one of which should be a reference model), expand the configurations covered, and will automatically select tests according to the model configuration.
The RISC-V ISA specification allows many architectural implementation choices. A tool has been created to describe implementation configurations (RISCV-CONFIG) that the RISCOF Framework will use to select and configure tests.
- Compatibility Test Framework v2.0 – GitHub Repository
- Compatibility Test Framework v3.0(beta) – GitHub Repository
- RISCV-CONFIG – Specification
Non-ISA Specifications
| Specification name | Version | Publish Date | Description | RISC-V Community | Source Repository |
|---|---|---|---|---|---|
| Efficient Trace for RISC-V | 2.0 | June 2022 | Specifies the signals between the RISC-V core and the encoder, compressed branch trace algorithm, and the packet format used to encapsulate the compressed branch trace information to implement processor tracing. | SOC Infrastructure Horizontal Committee | riscv-non-isa/tech-trace-spec |
| RISC-V External Debug Support | 0.13.2 | March 2019 | Outlines a standard architecture for external debug support on RISC-V platforms. | SOC Infrastructure Horizontal Committee | riscv/tech-debug-spec |
| RISC-V Supervisor Binary Interface Specification | 1.0.0 | May 2022 | Describes the RISC-V Supervisor Binary Interface, known from here on as SBI which enables supervisor-mode (S-mode or VS-mode) software to be portable across all RISC-V implementations by defining an abstraction for platform (or hypervisor) specific functionality. | Privileged Software Horizontal Committee | riscv-non-isa/riscv-sbi-doc |
| RISC-V UEFI Protocol Specification | 1.0.0 | May 2022 | Details all new UEFI protocols required only for RISC-V platforms. | Privileged Software Horizontal Committee | riscv-non-isa/riscv-uefi |
Note: If you do not see a specification in the above table, visit the RISC-V GitHub riscv-non-isa organization to see a complete list of all specifications which have been developed or are presently under development.
Compatibility Test Framework
The RISC-V Architectural Compatibility Test Framework Version 2 is now available. This framework compares arbitrary models against a reference signature, and currently covers RV[32|64]IMC unprivileged specifications only. Tests for the not-yet-ratified Crypto Scalar extension and RV32EMC extensions are also available.
Work on Version 3.0 framework (RISCOF) is underway which will compare two arbitrary models against each other (one of which should be a reference model), expand the configurations covered, and will automatically select tests according to the model configuration.
The RISC-V ISA specification allows many architectural implementation choices. A tool has been created to describe implementation configurations (RISCV-CONFIG) that the RISCOF Framework will use to select and configure tests.
- Compatibility Test Framework v2.0 – GitHub Repository
- Compatibility Test Framework v3.0(beta) – GitHub Repository
- RISCV-CONFIG – Specification
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