RISC-V International
Page History
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| Specification name | Version | Publish Date | Description | RISC-V Community | Source Repository |
|---|---|---|---|---|---|
| Efficient Trace for RISC-V | 2.0 | June 2022 | Specifies the signals between the RISC-V core and the encoder, compressed branch trace algorithm, and the packet format used to encapsulate the compressed branch trace information to implement processor tracing. | SOC Infrastructure Horizontal Committee | riscv-non-isa/tech-trace-spec |
| RISC-V ABIs Specification | 1.0 | November 2022 | Provides the processor-specific application binary interface document for RISC-V | Application & Tools Horizontal Committee | riscv-non-isa/riscv-elf-psabi-doc |
| RISC-V External Debug Support | 0.13.2 | March 2019 | Outlines a standard architecture for external debug support on RISC-V platforms. | SOC Infrastructure Horizontal Committee | riscv/tech-debug-spec |
| RISC-V Supervisor Binary Interface Specification | 1.0.0 | May 2022 | Describes the RISC-V Supervisor Binary Interface, known from here on as SBI which enables supervisor-mode (S-mode or VS-mode) software to be portable across all RISC-V implementations by defining an abstraction for platform (or hypervisor) specific functionality. | Privileged Software Horizontal Committee | riscv-non-isa/riscv-sbi-doc |
| RISC-V UEFI Protocol Specification | 1.0.0 | May 2022 | Details all new UEFI protocols required only for RISC-V platforms. | Privileged Software Horizontal Committee | riscv-non-isa/riscv-uefi |
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