Page History

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• Current Charter at https://github.com/riscv/groups/tree/main/Fast-Interrupts 
• Calendar: https://calendar.google.com/calendar/u/0/embed?src=tech.meetings@riscv.org
• Develop a low-latency, vectored, priority-based, preemptive interrupt scheme for interrupts directed to a single hart, compatible with the existing RISC-V standards. Provide both hardware specifications and software ABIs/APIs. Standardize compiler conventions for annotating interrupt handler functions.
• Meetings Disclaimers Video

Specification

• Latest Draft Fast Interrupt Specification (v0.9-draft-20211109)20220510)

  • issue #235 - change “exception” to “trap” to match priv spec wording.

  • issue #233 - mnxti pseudo-code clarification (added meaning of clic.priv,clic.level,clic.id)

  • issue #225 - bounded time to respond to interrupts

  • 11/09/2021 issue #48 - indicate when edge-triggered interrupts are cleared
  • 11/09/2021 issue #179 - set interrupt bit during nxti access

• What's next:
  • 41 outstanding issues. 
    • 31 active spec issues.
      • 1 issue (new CSR address) dependent on opcode review
    • 5 issues to track Definition of Done tasks
    • 5 issues kept open for future enhancements (post rev1.0)
    23 outstanding issues to be addressed.
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Encoding/OpCode consistency review

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Software

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