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Comment: issue status updated



  • Latest Draft Fast Interrupt Specification (v0.9-draft-20211109)
  • 11/09/2021 issue #48 - indicate when edge-triggered interrupts are cleared
  • 11/09/2021 issue #179 - set interrupt bit during nxti access20220510)
    • issue #235 - change “exception” to “trap” to match priv spec wording.
    • issue #233 - mnxti pseudo-code clarification (added meaning of clic.priv,clic.level,clic.id)
    • issue #225 - bounded time to respond to interrupts
  • What's next:
    • 23 outstanding issues to be addressed.41 outstanding issues. 
      • 31 active spec issues.
        • 1 issue (new CSR address) dependent on opcode review
      • 5 issues to track Definition of Done tasks
      • 5 issues kept open for future enhancements (post rev1.0)  

Encoding/OpCode consistency review


Project NameBase ArchitectureLevel of implementationNotes
area-optimized coreRV32/64

RTL simulation, FPGA Implementation, Synthesis

closed / commercial source   https://www.seagate.com/innovation/risc-v/
high-performance coreRV32RTL simulation, FPGA Implementation, Synthesisclosed / commercial source   https://www.seagate.com/innovation/risc-v/
microcontroller-class coreRV32IMAFCRTL, fully synthesizableApache License, Version 2.0 https://github.com/T-head-Semi/opene906/blob/main/doc/opene906_datasheet.pdf
E2/S2 seriesRV32/64RTL, fully synthesizablehttps://www.sifive.com/core-designer
N22RV32RTL, fully synthesizablehttp://www.andestech.com/en/products-solutions/andescore-processors/riscv-n22/
BM-310/BI-651RV32/64RTL, fully synthesizablehttps://cloudbear.ru/bm_310.html      https://cloudbear.ru/bi_651.html
n200/n900/nx900/ux900RV32/64RTL, fully synthesizable  (ECLIC)https://www.nucleisys.com/product.php?site=n200      https://www.nucleisys.com/product.php?site=n900