Page History

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• Current Charter at https://github.com/riscv/groups/tree/main/Fast-Interrupts 
• Calendar: https://calendar.google.com/calendar/u/0/embed?src=tech.meetings@riscv.org
• Develop a low-latency, vectored, priority-based, preemptive interrupt scheme for interrupts directed to a single hart, compatible with the existing RISC-V standards. Provide both hardware specifications and software ABIs/APIs. Standardize compiler conventions for annotating interrupt handler functions.
• Meetings Disclaimers Video

Specification

• Latest Draft Fast Interrupt Specification (v0.9-draft-20211221)
• 12/21/2021 issue #109 - add smclic arch string to spec
12/21/2021 issue #180 - change processor references to hart20221108)

• What's next:

  • 24 outstanding issues to be addressed.  .
    • 12 active spec issues.
      • big items: hypervisor, cliccfg reformat proposal
    • 6 issues to track Definition of Done tasks
    • 6 issues kept open for future enhancements (post rev1.0) 

Encoding/OpCode consistency review

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• Regular C function that save/restores all caller-save registers
• Inline handler gcc interrupt attribute to always callee-save every register (save as you go)EABI Task Group - improve interrupt latency by reducing the number of caller-save registers
• psABI Task Group - https://github.com/riscv-non-isa/riscv-elf-psabi-doc
  • https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/eabi/eabi.adoc