Page History

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• Copy  Non-ISA Platform Ratification Template 
• keep specification status spreadsheet up-to-date ( projected dates, DoD component effort sizing, DoD tasks your group needs resource help with,...)
• Keep dashboard  Non-ISA Extensions On Deck for Freeze Milestone up-to-date
• Develop final charter and plan with the group and send to Chairs (tech-chairs@lists.riscv.org) for approval within 4 weeks
• Fill in DoD Plan tab in checklist and send to chairs for approval of any deliverables that don't match the defaults along with any requested waivers
• Freeze-time preliminary POC definition approved by IC
• Develop Rationale document and send to chairs for approval
• Notify TSC and Chairs when you complete this milestone and include any waivers and an updated DoD spreadsheet.
• Plan: RISCV has prioritized RVA22.  expect CLIC to possibly be ratified with RVM22 RVM23 with other embedded extensions like Zfinx, new compressed, rv32e, p-extension.  So CLIC still on roadmap but probably next gen RISC-V grouping.  Continue working on issues and refining spec.
• Hypervisor support? One simple option is CLIC doesn’t work with H?  Both CLIC and AIA are evolving.  CLIC problematic places: table read hardware vectoring.  Otherwise no real complication.  If systems have both AIA and CLIC, how would it work. Maybe don’t need to worry about it?
• Impact of N-extension on CLIC?  Update CLIC spec to not rely on N-extension but add commentary on if N-extension is ratified how it would work with CLIC.

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• Current Charter at https://github.com/riscv/groups/tree/main/Fast-Interrupts 
• Calendar: https://calendar.google.com/calendar/u/0/embed?src=tech.meetings@riscv.org
• Develop a low-latency, vectored, priority-based, preemptive interrupt scheme for interrupts directed to a single hart, compatible with the existing RISC-V standards. Provide both hardware specifications and software ABIs/APIs. Standardize compiler conventions for annotating interrupt handler functions.

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