RISC-V International
Status at a glance:
- Current Definition-of-Done Status: kickoff DoD status directory
- Next Definition-of-Done Status: Plan
Specification
- Latest Draft Fast Interrupt Specification (v0.9-draft-20210406)
- What's next:
- 35 outstanding issues to be addressed.
Encoding/OpCode consistency review
- CSR Registers and addresses to be proposed
- What's next:
Architecture Tests
Compilers / Toolchains
TBD
GCC and Binutils
- TBD
LLVM
- TBD
Simulators
Though all listed under "simulators", these are actually a collection of formal model / virtual machine / architectural simulators / DV simulators etc.
SAIL
- TBD
Spike
- TBD
riscvOVPSimPlus
- Imperas Commercial Simulator
- Freeware version
- Support for:
QEMU
- QEMU implementation of CLIC-0.9 specification (Version 0.9-draft-20210217)
Proof-of-Concept implementations
Hardware
| Project Name | Base Architecture | Level of implementation | Notes |
|---|---|---|---|
| area-optimized core | RV32/64 | RTL simulation, FPGA Implementation, Synthesis | closed / commercial source https://www.seagate.com/innovation/risc-v/ |
| high-performance core | RV32 | RTL simulation, FPGA Implementation, Synthesis | closed / commercial source https://www.seagate.com/innovation/risc-v/ |
Software
| Project/Maintainer | Description |
|---|---|
ABI Extensions
- Regular C function that save/restores all caller-save registers
- Inline handler gcc interrupt attribute to always callee-save every register (save as you go)
- EABI Task Group - improve interrupt latency by reducing the number of caller-save registers
Overview
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