Status at a glance:
- Develop final charter and plan with the group and send to Chairs (firstname.lastname@example.org) for approval within 4 weeks
- Fill in DoD Plan tab in checklist and send to chairs for approval of any deliverables that don't match the defaults along with any requested waivers
- Freeze-time preliminary POC definition approved by IC
- Fill in task group and specification status spreadsheet information including extension or extension group names, projected dates, DoD component effort sizing, DoD tasks your group needs resource help with,...
- Develop Rationale document and send to chairs for approval
- Notify TSC and Chairs when you complete this milestone and include any waivers and an updated DoD spreadsheet.
- Develop a low-latency, vectored, priority-based, preemptive interrupt scheme for interrupts directed to a single hart, compatible with the existing RISC-V standards. Provide both hardware specifications and software ABIs/APIs. Standardize compiler conventions for annotating interrupt handler functions.
Encoding/OpCode consistency review
- Need to propose new CLIC CSR Registers and addresses
- What's next: when outstanding issues are reduced, start planning for review
- Test plan for the fast-interrupt is available.
- YAML config needs to be created. See info here.
GCC and Binutils
- No new instructions are added. Needs to be aware CSR names? Need to choose arch string like ziclic
- No new instructions are added. Needs to be aware of CSR names?
Though all listed under "simulators", these are actually a collection of formal model / virtual machine / architectural simulators / DV simulators etc.
ABI Extensions (no new ABI required)
- Regular C function that save/restores all caller-save registers
- Inline handler gcc interrupt attribute to always callee-save every register (save as you go)
- EABI Task Group - improve interrupt latency by reducing the number of caller-save registers