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Status at a glance:

To Reach Definition-of-Done Plan status: extension lifecycle and milestone definitions

  • Develop final charter and plan with the group and send to Chairs (tech-chairs@lists.riscv.org) for approval within 4 weeks
  • Fill in DoD Plan tab in checklist and send to chairs for approval of any deliverables that don't match the defaults along with any requested waivers
  • Freeze-time preliminary POC definition approved by IC
  • Fill in task group and specification status spreadsheet information including extension or extension group names, projected dates, DoD component effort sizing, DoD tasks your group needs resource help with,...
  • Develop Rationale document and send to chairs for approval
  • Notify TSC and Chairs when you complete this milestone and include any waivers and an updated DoD spreadsheet.

Charter

Specification

Encoding/OpCode consistency review

  • Need to propose new CLIC CSR Registers and addresses
  • What's next: when outstanding issues are reduced, start planning for review

Architecture Tests

  • Deterministic Test plan for the fast-interrupt is available.  Discussion on-going on how to add async/undeterministic testing of interrupts.
  • YAML config needs to be created.  See info here.
  • Discussion in Arch tests group to add automation (docker?) to validate check-in so that arch-test-suite is run against sail, spike, gcc/toolchain, with versions used recorded.  So sail and spike will need to work for CLIC before CLIC tests can be added to riscv-config github.

Compilers / Toolchains

GCC and Binutils

  • No new instructions are added.  Needs to be aware CSR names?  Need to choose arch string like ziclic

LLVM

  • No new instructions are added.  Needs to be aware of CSR names? 

Simulators

Though all listed under "simulators", these are actually a collection of formal model / virtual machine / architectural simulators / DV simulators etc.

SAIL

Spike

  • TBD

riscvOVPSimPlus

QEMU

Proof-of-Concept implementations

Hardware

Project NameBase ArchitectureLevel of implementationNotes
area-optimized coreRV32/64

RTL simulation, FPGA Implementation, Synthesis

closed / commercial source   https://www.seagate.com/innovation/risc-v/
high-performance coreRV32RTL simulation, FPGA Implementation, Synthesisclosed / commercial source   https://www.seagate.com/innovation/risc-v/




















Software

Project/MaintainerDescription






ABI Extensions (no new ABI required)

  • Regular C function that save/restores all caller-save registers
  • Inline handler gcc interrupt attribute to always callee-save every register (save as you go)
  • EABI Task Group - improve interrupt latency by reducing the number of caller-save registers
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