RISC-V extension and feature support

This page gives an overview of the extension and feature support in the RISC-V SW ecosystem.

Published specifications can be found here: https://riscv.org/technical/specifications/

The main repository of the ISA specifications is: https://github.com/riscv/riscv-isa-manual

Certain extensions are generated by individual TGs.

An overview of the current status of unratified extensions can be found here: Architecture Review

mainline...SW support has been merged into the main development branch of the corresponding SW project
staging branch...SW support lives in a staging branch and is not mainlined
PR...SW support exists in form of a pull request for mainline (in-review or waiting for ratification)
n/a...not applicable, not relevant, or not required
missing...currently no known implementation
dev:X...feature is in development by X
empty cells...unknown status (feel free to share your knowledge)

ISA extension naming conventions

E.g.: RV64I1p0M1p0A1p0F1p0D1p0 or RV32I2_M2_A2 (P extension requires underscore!)

The complete ISA extension naming convention can be found in the unpriv specification.

Extensions with prefix Z...standard user-level
Extensions with prefix X...non-standard user-level
Extensions with prefix S...standard supervisor-level
Extensions with prefix SX...non-standard supervisor-level