RISC-V extension and feature support in the Open Source SW Ecosystem

This page gives an overview of the extension and feature support in the RISC-V SW ecosystem.

Overview

• This page only tracks extensions and features that are specified by groups (TGs, HCs) of RISC-V International.
• The extensions and features are grouped by their specification's state.
• Published (official) specifications can be found here: https://riscv.org/technical/specifications/
• The main repository of the ISA specifications is: https://github.com/riscv/riscv-isa-manual
• The On Deck Dashboards lists the specifications that are frozen and ready for ratification

Published specifications (20191213)

• The RISC-V Instruction Set Manual, Volume I: User-Level ISA, Document Version 20191213
• The RISC-V Instruction Set Manual, Volume II: Privileged Architecture, Document
  Version 20190608-Priv-MSU-Ratified

The table below lists the status of the extensions and features of above listed published extensions.

upstream...SW support has been merged into the main development branch of the corresponding SW project
staging branch...SW support lives in a staging branch and is not upstreamed
PR...SW support exists in form of a pull request for upstream (in-review or waiting for ratification)
n/a...not applicable, not relevant, or not required
missing...currently no known implementation
dev:X...feature is in development by X
empty cells...unknown status (feel free to share your knowledge)

ISA extension naming conventions

E.g.: RV64I1p0M1p0A1p0F1p0D1p0 or RV32I2_M2_A2 (P extension requires underscore!)

The complete ISA extension naming convention can be found in the unpriv specification.

Extensions with prefix Z...standard user-level
Extensions with prefix X...non-standard user-level
Extensions with prefix S...standard supervisor-level
Extensions with prefix SX...non-standard supervisor-level