Status at a glance:
Specification
Encoding/OpCode consistency review
- CSR Registers and addresses to be proposed
Architecture Tests
- Test plan for the fast-interrupt is available.
- YAML config needs to be created. See here.
Compilers / Toolchains
TBD
GCC and Binutils
LLVM
Simulators
Though all listed under "simulators", these are actually a collection of formal model / virtual machine / architectural simulators / DV simulators etc.
SAIL
Spike
riscvOVPSimPlus
QEMU
Proof-of-Concept implementations
Hardware
Project Name | Base Architecture | Level of implementation | Notes |
---|
| RV32/64 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Software
Project/Maintainer | Description |
---|
|
|
|
|
|
|
ABI Extensions