Status at a glance:

To Reach Definition-of-Done Plan status: extension lifecycle and milestone definitions

Charter

Specification

Encoding/OpCode consistency review

Architecture Tests

Compilers / Toolchains

GCC and Binutils

LLVM

Simulators

Though all listed under "simulators", these are actually a collection of formal model / virtual machine / architectural simulators / DV simulators etc.

SAIL

Spike

riscvOVPSimPlus

QEMU

Proof-of-Concept implementations

Hardware

Project NameBase ArchitectureLevel of implementationNotes
area-optimized coreRV32/64

RTL simulation, FPGA Implementation, Synthesis

closed / commercial source   https://www.seagate.com/innovation/risc-v/
high-performance coreRV32RTL simulation, FPGA Implementation, Synthesisclosed / commercial source   https://www.seagate.com/innovation/risc-v/




















Software

Project/MaintainerDescription






ABI Extensions (no new ABI required)