Status at a glance:

To Reach Definition-of-Done Plan status: extension lifecycle and milestone definitions

Charter

Specification

Encoding/OpCode consistency review

Architecture Tests

Compilers / Toolchains

GCC and Binutils

LLVM

Simulators

Though all listed under "simulators", these are actually a collection of formal model / virtual machine / architectural simulators / DV simulators etc.

SAIL

Spike

riscvOVPSimPlus

QEMU

Proof-of-Concept implementations

Hardware

Project NameBase ArchitectureLevel of implementationNotes
area-optimized coreRV32/64

RTL simulation, FPGA Implementation, Synthesis

closed / commercial source   https://www.seagate.com/innovation/risc-v/
high-performance coreRV32RTL simulation, FPGA Implementation, Synthesisclosed / commercial source   https://www.seagate.com/innovation/risc-v/
microcontroller-class coreRV32IMAFCRTL, fully synthesizableApache License, Version 2.0 https://github.com/T-head-Semi/opene906/blob/main/doc/opene906_datasheet.pdf
E2/S2 seriesRV32/64RTL, fully synthesizablehttps://www.sifive.com/core-designer
N22RV32RTL, fully synthesizablehttp://www.andestech.com/en/products-solutions/andescore-processors/riscv-n22/
BM-310/BI-651RV32/64RTL, fully synthesizablehttps://cloudbear.ru/bm_310.html      https://cloudbear.ru/bi_651.html
n200/n900/nx900/ux900RV32/64RTL, fully synthesizable  (ECLIC)https://www.nucleisys.com/product.php?site=n200      https://www.nucleisys.com/product.php?site=n900

Software

Project/MaintainerDescription






ABI Extensions (no new ABI required)