What's next:
Major items on Freeze Checklist:
SAIL Implementation Completed
ACT tests created. Missing SHV tests.
riscv-software-src/riscv-config: RISC-V Configuration Validator (github.com)
Schema_isa.yaml - gives allowed configuration on risc-v and allowed values. WARL fields give allowed ranges. 10k lines in file.
Examples/rivc32i_isa.yaml is compared against schema_isa.yaml to see if it is allowed.
When add new CSRs, add PR to add to schema_isa.yaml and then will be checked against example implementation.
Schemas/schema_platforml.yaml - memory mapped registers (like clicintctl, etc.)
Run python scripts that look at your implementation and see if it is valid. e.g., if have d then have f- extenstion, etc. checks if WARL field is valid.
Write anything, read legal. mapping from what is illegal to what is legal. mapping is arbitrary. so prefer (easiest) if implementers implement when write something illegal, don’t write. that works easiest for describing in this file.
Though all listed under "simulators", these are actually a collection of formal model / virtual machine / architectural simulators / DV simulators etc.
Project Name | Base Architecture | Level of implementation | Notes |
---|---|---|---|
area-optimized core | RV32/64 | RTL simulation, FPGA Implementation, Synthesis | closed / commercial source https://www.seagate.com/innovation/risc-v/ |
high-performance core | RV32 | RTL simulation, FPGA Implementation, Synthesis | closed / commercial source https://www.seagate.com/innovation/risc-v/ |
microcontroller-class core | RV32IMAFC | RTL, fully synthesizable | Apache License, Version 2.0 https://github.com/T-head-Semi/opene906/blob/main/doc/opene906_datasheet.pdf |
E2/S2 series | RV32/64 | RTL, fully synthesizable | https://www.sifive.com/core-designer |
N22 | RV32 | RTL, fully synthesizable | http://www.andestech.com/en/products-solutions/andescore-processors/riscv-n22/ |
BM-310/BI-651 | RV32/64 | RTL, fully synthesizable | https://cloudbear.ru/bm_310.html https://cloudbear.ru/bi_651.html |
n200/n900/nx900/ux900 | RV32/64 | RTL, fully synthesizable (ECLIC) | https://www.nucleisys.com/product.php?site=n200 https://www.nucleisys.com/product.php?site=n900 |
R9A02G021 | RV32 | samples available | R9A02G021 Datasheet (renesas.com) |
Project/Maintainer | Description |
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