Lightweight instruction set extensions for RV32 and RV64 HARTs. Proposed extensions:
| Who | What | Status | Task |
|---|---|---|---|
| PLCT | GCC | Not started | Update extension names: Zkb → Zbkb etc. |
| PLCT | GCC | Not started | Update aes32/64* encodings if applicable. |
| PLCT | LLVM | Done | Update extension names: Zkb → Zbkb etc. |
| PLCT | LLVM | Done | Update aes32/64* encodings if applicable. |
| IIT | riscv-config | Not started | Update extension names: Zkb → Zbkb etc. |
| IIT | riscv-config | Not started | Update instruction inclusion in different extensions |
| IIT | riscv-arch-tests | Not started | Break up K suite into Zk* extensions |
| IIT | riscv-arch-tests | Not started | Update instruction inclusion in different extensions |
Imperas maintain pre-built toolchains for various in-progress RISC-V extensions here. See the "rvk-*" branches for scalar crypto.
Though all listed under "simulators", these are actually a collection of formal model / virtual machine / architectural simulators / DV simulators etc.
| Project Name | Base Architecture | Level of implementation | Notes |
|---|---|---|---|
| Stand-alone functional units | RV32/64 | Yosys Synthesis | Stand-alone functional-unit style implementations of the dedicated scalar crypto instructions. Free to use as "drop-ins" for prototyping. |
| scarv-cpu | RV32 | Behavioural RTL simulation / Yosys Synthesis / FPGA | Completely Public/Open Source. Useful as a public baseline. Commercial implementations should aim to be better than this! |
| PQShield security core | RV32 | (assumed) Behavioural RTL simulation. Running on FPGA. | Closed / commercial source - PQShield. |
| Minidice TRNG | N/A | FPGA Implementation | Closed / commercial source - PQShield. Complete implementation of the RISC-V entropy source. |
| Romain Dolbeau / VexRISC-V | RV32 | Running on FPGA. | Uses VexRiscv core as a base. Completely independent implementation from scratch, outside the Crypto TG. |
| IQonIC Works RV32IC_P5 | RV32 | In development | "implemented Zkn (...), along with selectable Zb* and Zkb. We also have an optional custom extension that does AES block encrypt/decrypt, and a bus-based AES/cipher-mode accelerator. Work in progress benchmarking them on FPGA to compare relative performance in accelerating crypto library functions." |
| croyde-riscv | RV64 | Behavioural RTL simulation / Yosys Synthesis / FPGA | 3-stage RV64 micro-controller. rv64imck. Free/Open source. Something commercial implementations should better. Implements everything except ZKR. |
We still need RV64 implementations. | Project/Maintainer | Description |
|---|---|
| Romain Dolbeau | Independent implementations of various important ciphers + modes of operation. |
| rvkrypto-fips / Markku | "FIPS 140-3 and higher-level algorithm Tests for RISC-V Crypto Extension" |
| riscv-crypto benchmarks | Initial benchmarks used to develop the scalar crypto extension. |