Lightweight instruction set extensions for RV32 and RV64 HARTs. Proposed extensions:
Project Name | Base Architecture | Level of implementation | Notes |
---|---|---|---|
scarv-cpu | RV32 | Behavioural RTL simulation. Running on FPGA. Post yosys synthesis results. | Completely Public/Open Source. Useful as a public baseline. Commercial implementations should aim to be better than this! |
PQShield security core | RV32 | (assumed) Behavioural RTL simulation. Running on FPGA. | Closed / commercial source. Most complete implementation of the entropy source. |
Romain Dolbeau / VexRISC-V | RV32 | Running on FPGA. | Uses VexRiscv core as a base. Completely independent implementation from scratch, outside the Crypto TG. |