Status at a glance:

Scalar Crypto Specification:

Lightweight instruction set extensions for RV32 and RV64 HARTs.  Proposed extensions:

Specification

Encoding/OpCode consistency review

Architecture Tests

GCC and Assembler

SAIL

Spike

LLVM

QEMU

Proof-of-Concept hardware implementations

Project NameBase ArchitectureLevel of implementationNotes
scarv-cpuRV32Behavioural RTL simulation. Running on FPGA. Post yosys synthesis results.

Completely Public/Open Source. Useful as a public baseline. Commercial implementations should aim to be better than this!

PQShield security coreRV32(assumed) Behavioural RTL simulation. Running on FPGA.Closed / commercial source. Most complete implementation of the entropy source.
Romain Dolbeau / VexRISC-VRV32Running on FPGA.Uses VexRiscv core as a base. Completely independent implementation from scratch, outside the Crypto TG.

ABI Extensions