RISC-V International
This page gives an overview of the extension and feature support in the RISC-V SW ecosystem.
Published specifications can be found here: https://riscv.org/technical/specifications/
The main repository of the ISA specifications is: https://github.com/riscv/riscv-isa-manual
Certain extensions are generated by individual TGs.
An overview of the current status of unratified extensions can be found here: Architecture Review
Extension / feature | Ratified? | HW exists (see also here)? | FPGA exists? | Spike | Qemu | Binutils | GCC | glibc | newlib | LLVM | OpenSBI | FreeBSD | Linux | GDB |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RV32I v2.1 | y | e.g. LowFive | e.g. Rocket | mainline | mainline | mainline | mainline | mainline | mainline | mainline | mainline | not supported | mainline | |
RV64I v2.1 | y | e.g. BeagleV | e.g. Rocket | mainline | mainline | mainline | mainline | mainline | mainline | mainline | mainline | mainline | mainline | |
Big-endian support | y | mainline | mainline | |||||||||||
RV32E v1.9 | n | mainline | not supported | not supported | not supported | |||||||||
M (Multiplication and Division) v2.0 | y | e.g. BeagleV | e.g. Rocket | mainline | mainline | mainline | mainline | n/a | n/a | mainline | n/a | n/a | n/a | |
A (Atomic) v2.1 | y | e.g. BeagleV | e.g. Rocket | mainline | mainline | mainline | mainline | n/a | n/a | mainline | mainline (atomics) | mainline (atomics) | mainline (atomics) | |
F (SP float) v2.2 | y | e.g. BeagleV | e.g. Rocket | mainline | mainline | |||||||||
D (DP float) v2.2 | y | mainline | mainline | |||||||||||
RVWMO v2.0 | y | e.g. BeagleV | e.g. Rocket | mainline (emulation is seq. consistent) | mainline (emulation is seq. consistent) | n/a | n/a | n/a | n/a | n/a | mainline (barriers and locks) | mainline (barriers and locks) | mainline (barriers and locks), but needs optimization | |
ABIs (ILP32, ILP32E, ILP32F, ILP32D, LP64, LP64f, LP64D, LP64Q) | Documented ABIs | ilp32, ilp32f, ilp32d, ilp32q, ilp32e, lp64, lp64f, lp64d, lp64q | ilp32, ilp32f, ilp32d, ilp32e, lp64, lp64f, lp64d | ilp32, ilp32d, lp64, lp64d | ilp32, ilp32f, ilp32d, ilp32e, lp64, lp64f, lp64d | ilp32, ilp32d, lp64, lp64d | n/a | lp64, lp64d | n/a | |||||
C (compressed) v2.0 | y | e.g. EH2 | mainline | mainline | mainline | mainline | n/a | n/a | mainline | mainline | ||||
Q (QP float) v2.2 | y | mainline | ||||||||||||
Zifencei v2.0 | y | e.g. EH2 | mainline | mainline | mainline | mainline | mainline | |||||||
Zihintpause v1.0 | mainline | |||||||||||||
Zicsr v2.0 | y | e.g. EH2 | mainline | mainline | mainline | mainline | mainline | |||||||
Counters v2.0 | n | mainline | mainline | n/a | n/a | n/a | mainline | mainline | ||||||
Machine ISA v1.11 (CSRs, ECALL, EBREAK, MRET/SRET/URET, WFI, Reset, NMIs, PMAs, PMP) | y | mainline | mainline | n/a | n/a | |||||||||
Supervisor ISA v1.11 (CSRs, SFENCE.VMA, Sv32/Sv39/Sv48) | y | mainline | mainline | n/a | ||||||||||
B (bitmanip) v0.92 (Zba, Zbb, Zbc, Zbe, Zbf, Zbk, Zbp, Zbr, Zbs) | n | e.g. PR for Rocket, | PR | dev branch | mainline (experimental) | |||||||||
K (scalar crypto) | n | PR | PR | |||||||||||
P (SIMD) v0.9.4 | n | mainline (but v0.9.2!) | Mailpatch (v0.9.4) | PR | PR | PR | ||||||||
V (vector) v0.10, Vector Extension Intrinsics, Vector Calling Convention | n | z.B. Allwinner D1 (but v0.7.1) | mainline | mainline (but v0.7.1) | mainline (experimental, Zvlsseg API not settled, FP16 ABI not settled) | |||||||||
Ztso v0.1 | n | |||||||||||||
Zam v0.1 | n | |||||||||||||
H (hypervisor) v0.6.1 | n | e.g. Rocket (PR) | mainline | mainline | dev branch | n/a | n/a | n/a | mainline | KVM patches on LKML | ||||
Zmmul v0.1 (subset of M) | ||||||||||||||
J (JIT/Java) | ||||||||||||||
TEE | ||||||||||||||
Snavpot | n | |||||||||||||
Zfinx | n | staging branch | staging branch | staging branch | staging-branch | PR | ||||||||
Z*inx (with new ABIs: ILP32X/LP64X) | dev: PLCT | dev: PLCT | PR | |||||||||||
Zfh | mainline | |||||||||||||
SV57 | ||||||||||||||
Zce | dev: PLCT | dev: PLCT | ||||||||||||
CMO / Zicmobase | n |
mainline...SW support has been merged into the main development branch of the corresponding SW project
staging branch...SW support lives in a staging branch and is not mainlined
PR...SW support exists in form of a pull request for mainline (in-review or waiting for ratification)
n/a...not applicable, not relevant, or not required
missing...currently no known implementation
dev:X...feature is in development by X
empty cells...unknown status (feel free to share your knowledge)
E.g.: RV64I1p0M1p0A1p0F1p0D1p0 or RV32I2_M2_A2 (P extension requires underscore!)
The complete ISA extension naming convention can be found in the unpriv specification.
Extensions with prefix Z...standard user-level
Extensions with prefix X...non-standard user-level
Extensions with prefix S...standard supervisor-level
Extensions with prefix SX...non-standard supervisor-level