RISC-V International
This page gives an overview of the extension and feature support in the RISC-V SW ecosystem.
Published specifications can be found here: https://riscv.org/technical/specifications/
The main repository of the ISA specifications is: https://github.com/riscv/riscv-isa-manual
Certain extensions are generated by individual TGs.
An overview of the current status of unratified extensions can be found here: Opcode and State Review
| Extension / feature | Ratified? | Spike | Qemu | Binutils | GCC | glibc | newlib | LLVM | OpenSBI | Linux |
|---|---|---|---|---|---|---|---|---|---|---|
| RV32I v2.1 | y | mainline | mainline | mainline | mainline | mainline | mainline | mainline | mainline | |
| RV64I v2.1 | y | mainline | mainline | mainline | mainline | mainline | mainline | mainline | mainline | |
| Big-endian support | y | mainline | ||||||||
| RV32E v1.9 | n | mainline | not supported | not supported | ||||||
| Zifencei v2.0 | y | n/a | ||||||||
| Zicsr v2.0 | y | |||||||||
| M v2.0 | y | |||||||||
| A v2.1 | y | mainline | mainline | mainline | mainline ( | |||||
| F v2.2 | y | |||||||||
| D v2.2 | y | |||||||||
| C v2.0 | y | mainline | mainline | |||||||
| Q v2.2 | y | |||||||||
| RVWMO v2.0 | y | mainline (emulation is seq. consistent) | mainline (emulation is seq. consistent) | |||||||
| Ztso v0.1 | n | |||||||||
| Zam v0.1 | n | |||||||||
| Machine ISA v1.11 (CSRs, ECALL, EBREAK, MRET/SRET/URET, WFI, Reset, NMIs, PMAs, PMP) | y | mainline | mainline | |||||||
| Supervisor ISA v1.11 (CSRs, SFENCE.VMA, Sv32/Sv39/Sv48) | y | mainline | mainline | |||||||
| ABIs (ILP32, ILP32E, ILP32F, ILP32D, LP64, LP64f, LP64D, LP64Q) | y | ilp32, ilp32d, lp64, lp64d | ilp32, ilp32d, lp64, lp64d | ilp32, ilp32d, lp64, lp64d | ilp32, ilp32d, lp64, lp64d | |||||
| Experimental ABIs | ||||||||||
mainline...SW support has been merged into the main development branch of the corresponding SW project
n/a...not applicable, not relevant or not required
empty cells...unknown status (feel free to share your knowledge)
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