Specification Status

Table of Contents

Overview

The RISC-V specification process is governed by the Ratification Policy and more concisely articulated in the Specification Lifecycle and Milestone Definitions presentation.  To help Task Group Chairs, Vice-chairs, and specification authors navigate this process, the RISC-V Lifecycle Guide has a whole section on "Specification Lifecycle" with an introductory section describing the process and subsections for each milestone that include step-by-step descriptions of the process.

This page serves as the starting point for understanding the status of specifications currently being developed by RISC-V.  This status is best represented as progress toward the key Specification Milestones (Plan, Freeze, and Ratification-ready) which are obtained sequentially.  Specific status for the relevant status columns is detailed in the Status Key section below.  The chairs and vice-chairs of Task Groups, specification authors, and Horizontal and ISA Committee chairs and vice-chairs jointly own ensuring their specifications are listed below and reflect accurate status.

In-process specifications are grouped below into two tables based on whether they impact the RISC-V ISA (In-process ISA Specifications) or not (In-process Non-ISA Specifications).  Items should have links to their respective specification repo (), Ratification Plan() if not a Fast-track item, and an Acceptance Criteria Status checklist (). 

Status of active votes by TSC and Committee Chairs can be found on the RISC-V Vote Status wiki page.

Completed specifications are tracked at the bottom of the page.

This dashboard does NOT intend to show detailed status (that's available in the status checklist for the specification, ), but rather the general status in the journey to ratification. 

NOTE: This page is managed by the RISC-V staff with assistance from each specification owner. To get updates to this page or for questions, contact help@riscv.org.

In-process ISA Specification Status

Ratification Package  : Project repo : Plan doc : Status chklist	extensions included	Task group approved by TSC date or Fast Track approved by AR date	Specification State****	ISA AR State++	Fast Track	Priv / Unpriv	Committee (Owner)	Task Group	Plan Milestone Target Date	Freeze Milestone Target Date	Ratification Milestone Target Date	Plan Milestone Next Step*	Freeze Milestone Next Step**	Ratification Milestone Next Step***	Last Updated	Notes	In RVA2023 profile as mandatory or supported optional	Migrated to Jira? Jira Link
Atomic compare-and-swap (CAS)	Zacas	10 Apr 2023	Stable	Approved (7/10/23)	Y	U	Unpriv IC (Ved, Greg)	N/A	Q2'23	Q3'23	Q4'23	complete	complete	public review complete	08 Sep 2023	AR approved.		Jira Link
Bfloat16	Zfbfmin, Zvfbfmin, Zvfbfwma		Plan Complete	Approved (7/15/23)	Y	U	Unpriv IC (Ken Dockser)	N/A	N/A	Q2'23		N/A	acceptance criteria complete		17 Jul 2023	AR approved.		Jira Link
Capacity and Bandwidth Controller QoS Register Interface (CBQRI)	Ssqosid	06 Oct 2022	Plan Complete	Queued	N	P	SOC Infrastructure HC (Eric Shiu, Ambika Krishnamoorthy)	CBQRI	4Q'22	Q2'23	Q3'23	complete	AR approval		16 Apr 2023	Submitted to AR		Jira link
Conditional Ops	Zicond	17 Oct 2022	Public Review Complete	Approved	Y	U	Unpriv IC (Philipp)	N/A	Q1'23	Q1'23	Q2'23	complete	complete	committee chair approval	07 Sep 2023			Jira link
Control Transfer Records	Smctr, Ssctr	07 Mar 2023	Plan Complete	Development	N	P	Priv IC (Beeman Strong)	CTR TG	Q2'23	Q3'23	Q4'23	complete	acceptance criteria complete		19 Jul 2023			Jira link
Counter Mode Filtering	Smcntrpmf	11 Feb 2023	Frozen	Approved	Y	U	Priv IC (Beeman Strong)	N/A	Q1'23	Q2'23	Q3'23	complete	complete	public review complete	02 Aug 2023			Jira Link
Debug	Sdext, Sdtrig	2020	Plan Complete	Development	N	P	Priv IC (Tim Newsome)	Debug TG	Q1'23	Q2'23	Q3'23	complete	acceptance criteria complete	start	29 Mar 2023	Waiver vote for SAIL and ACT	n	Jira link
Fast Interrupt	Smclic, Ssclic, Suclic, Smclicshv, Smclicconfig	2020	Plan Complete	Development	N	P	Priv IC (Dan Smathers)	Fast Interrupts	N/A	Q3'23		N/A	spec development - stable	start	18 Jan 2023		n	Jira link
Hardware Updating of PTE A/D Bits	Svadu	17 Oct 2022	Public Review Started	Approved	Y	P	Priv IC (Ved Shanbhogue)	N/A	N/A	Q2'23	Q3'23	N/A	complete	public review complete	29 Aug 2023	Public Review ends Sept 28.	y	Jira link
Indirect CSR Access	Smcsrind, Sscsrind		Stable	Approved	Y	P	Priv IC (Beeman Strong)	N/A	Q3'23			complete	acceptance criteria complete		23 Aug 2023			Jira link
Instruction/Data Consistency	Zjid	2020	Stable	Development	N	P	Priv IC (Martin Maas)	I/D Consistency	N/A	Q2'23		N/A - Grandfathered	AR approval	start	06 Apr 2023	Spec in slide form, needs to be translated into write-up.	?	Jira link
"May Be Ops" (for CFI, etc.)	Zimop, Zcmop	17 Oct 2022	Plan Complete	Development	Y	U	Unpriv IC (Andrew Waterman)	N/A	N/A	Q2'23		N/A	AR approval	start	07 Mar 2023	Andrew working with Ved and ARC on new design Potential ABI impacts identified by ARC.	n	Jira Link
Packed SIMD	Zbpbo, Zpn, Zpsfoperand, P	2020	New	Development	N	U	Unpriv IC (Kevin Chen)	Packed SIMD	Q3'23	Q4'23	Q4'23	start	start	start	22 Feb 2023	Need plan from Kevin Chen	n	Jira Link
Pointer masking	Ssnjpm, Smnjpm, Smmjpm	2020	Stable	Reworking	N	P	Priv IC (Martin Maas)	Pointer Masking	Q1'23	Q2'23		complete	AR approval	start	28 Feb 2023	Ongoing discussion with ARC around design.	?	Jira Link
Priv 1.13			New	Development	N	P	Priv IC (TBD)					build plan			10 Apr 2023	Awaiting guidance from Greg and Andrew.	y	Jira Link
Resumable Non-maskable Interrupts	Smrnmi	17 Oct 2022	Plan  Complete	Reviewing	Y	P	Priv IC (Andrew Waterman)	N/A	N/A	Q1'23		N/A	acceptance criteria complete	start	15 Mar 2023	Status checklist reviewed by Philipp.  Work needed.  Requested owner from Greg and Andrew (Priv IC).	n	Jira Link
Shadow Stacks and Landing Pads	Zicfiss, Zicfilp	11 Aug 2022	Plan  Complete	Queued	N	U + P	Unpriv IC + Priv IC (George, Ved)	SS-LP-CFI	Q4'22	Q3'23	Q3'23	Complete	AR approval	start	22 Apr 2023	Submitted to AR	n	Jira Link
Supervisor Counter Delegation	Smcdeleg, Ssccfg	31 Jan 2023	Stable	Queued	Y	P	Priv IC (Beeman Strong)	N/A (Fast Track)	Q1'23	Q2'23	Q3'23	Complete			21 Feb 2023	Needs TSC notification of Plan Milestone Submitted to AR		Jira Link
Supervisor Memory Tracking Table (SmMTT)	Smmtt		Plan Complete		N	P	Priv IC (Ravi Sahita)	SmMTT	Q3'23			Complete	acceptance criteria complete		23 Aug 2023			Jira Link
S-mode PMP	Sspmp	29 Aug 2022	Plan  Complete	Development	N	P	Security HC (Dong Du)	S-Mode Physical Memory Protection	Q1'23	Q3'23	Q4'23	Complete	Start	N/A	22 Feb 2023	Plan Milestone review 2/15	n	Jira Link
Vector Crypto - all-rounds AES	Zvknf	04 May 2022	Stable	Development	N	U	Unpriv IC (TBD)	Cryptographic Extensions	3Q'22	TBD	YE2024	Complete	AR Approval	start	07 Feb 2023	No owner to drive work.	n	Jira Link

In-process Non-ISA Specification Status

Status Key

The following steps and associated next sequential steps for the milestones listed in the tables above may be parallelized at times, but are most simply thought of as a sequential set.  All previous steps are done.  For more details on each step,  see the RISC-V Lifecycle Guide section on "Specification Lifecycle" and it's specific subsections for each milestone, including step-by-step descriptions.

The usable Milestone next Steps are as follows:

* Plan Milestone next Steps:

1. build plan
2. review by chairs
3. complete (nothing else to do)

** Freeze Milestone next step:

1. start
2. spec development - stable
3. AR approval (ISA/SW AR)
4. acceptance criteria complete (including waivers, or approval)
5. committee chair approval
6. freeze
7. complete (nothing else to do)

*** Ratification Milestone next step (don't start until freeze is complete):

1. start
2. send out for public review
3. public review complete
4. acceptance criteria complete 
5. committee chair approval
6. TSC approval
7. BOD approval
8. ratified
9. complete (nothing else to do)

++ ISA AR State (owner)

1. Development (not ready for AR) (TG/IC)
2. Queued (AR)
3. Reviewing (AR)
4. Reworking (if necessary as a result of the review after complete goes back to the queue) (TG/IC)
5. Approved (AR)

NOTE: Some Milestone next steps may be marked as "N/A" for "Not Applicable" with an explanation after a trailing "-".  For example, "N/A - Grandfathered" means that the step was skipped due to the fact that the process changed after the step would have been completed and it has been "Grandfathered" in (meaning accepted as N/A) as acceptable.

**** Specification State values:

1. New
2. Plan Complete
3. Stable
4. Frozen
5. Public Review Started
6. Public Review Complete
7. TSC Approved
8. Ratified

Previously Ratified Specifications

2023

ISA Specifications

Non-ISA Specifications

2022

ISA Specifications

Non-ISA Specifications

2021