RISC-V International

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Comment: updated hypervisor notes, added T-head XuanTie E906 to proof of concept table, updated CLIC arch string possible name


  • Copy  Non-ISA Platform Ratification Template 
  • keep specification status spreadsheet up-to-date ( projected dates, DoD component effort sizing, DoD tasks your group needs resource help with,...)
  • Keep dashboard  Non-ISA Extensions On Deck for Freeze Milestone up-to-date
  • Develop final charter and plan with the group and send to Chairs (tech-chairs@lists.riscv.org) for approval within 4 weeks
  • Fill in DoD Plan tab in checklist and send to chairs for approval of any deliverables that don't match the defaults along with any requested waivers
  • Freeze-time preliminary POC definition approved by IC
  • Develop Rationale document and send to chairs for approval
  • Notify TSC and Chairs when you complete this milestone and include any waivers and an updated DoD spreadsheet.
  • Plan: RISCV has prioritized RVA22.  expect CLIC to possibly be ratified with RVM23 with other embedded extensions like Zfinx, new compressed, rv32e, p-extension.  So CLIC still on roadmap but probably next gen RISC-V grouping.  Continue working on issues and refining spec.
  • Hypervisor support? One simple option is CLIC doesn’t work with H?  Both CLIC and AIA are evolving.  CLIC problematic places: table read hardware vectoring.  Otherwise no real complication.  If systems have both AIA and CLIC, how would it work. Maybe don’t need to worry about it?
    • See issue #92 discussion.  Lastest discussion: The AIA spec is being developed to be the standard support for interrupts for standard hypervisors. Possible hypervisor directions for fast interrupts for embedded include: 1) a minimal CLIC extension that adds HS mode as another privilege layer in the stack, so the hypervisor could optionally receive interrupts and optionally enable/hide interrupts from lower privilege modes. This would allow the 2-stage translation and other features of the hypervisor to be used in a CLIC-based system, but would not support sending interrupts directly to descheduled guest OS contexts (have to route via hypervisor interrupt). 2) support multiple descheduled CLIC contexts to which interrupts could be sent directly while they were sleeping, which would be a much bigger project. 3) add an extension to AIA (instead of working on CLIC) to somehow reduce interrupt latency using the standard hypervisor stack.
  • Impact of N-extension on CLIC?  Update CLIC spec to not rely on N-extension but add commentary on if N-extension is ratified how it would work with CLIC.


  • No new instructions are added.  Needs to be aware CSR names?  Need to choose arch string like ziclicGiven that the key CSRs are in M-mode, it should probably be named something like "Smclic"


  • No new instructions are added.  Needs to be aware of CSR names? 


Project NameBase ArchitectureLevel of implementationNotes
area-optimized coreRV32/64

RTL simulation, FPGA Implementation, Synthesis

closed / commercial source   https://www.seagate.com/innovation/risc-v/
high-performance coreRV32RTL simulation, FPGA Implementation, Synthesisclosed / commercial source   https://www.seagate.com/innovation/risc-v/
microcontroller-class coreRV32IMAFCRTL, fully synthesizableApache License, Version 2.0 https://github.com/T-head-Semi/opene906/blob/main/doc/opene906_datasheet.pdf