Status at a glance:



  • Latest Draft Fast Interrupt Specification (v0.9-draft-20240314)
  • What's next:
    • 0 outstanding pre-ratification issues.
      • Freeze Checklist Completed
    • Major items on Freeze Checklist: 

      • RISC-V SAIL 

      SAIL Implementation Completed 

      • RISC-V Tests 

      ACT tests created.  Missing SHV tests.

      • RISC-V Tests Input 

      riscv-software-src/riscv-config: RISC-V Configuration Validator ( 

      Schema_isa.yaml - gives allowed configuration on risc-v and allowed values.  WARL fields give allowed ranges.  10k lines in file. 

      Examples/rivc32i_isa.yaml is compared against schema_isa.yaml to see if it is allowed. 

      When add new CSRs, add PR to add to schema_isa.yaml and then will be checked against example implementation. 

      Schemas/schema_platforml.yaml - memory mapped registers (like clicintctl, etc.) 

      Run python scripts that look at your implementation and see if it is valid.  e.g., if have d then have f- extenstion, etc. checks if WARL field is valid. 

      Write anything, read legal.  mapping from what is illegal to what is legal.  mapping is arbitrary.  so prefer (easiest) if implementers implement when write something illegal, don’t write.  that works easiest for describing in this file. 

Encoding/OpCode consistency review

  • Need to propose new CLIC CSR Registers and addresses
  • What's next: when outstanding issues are reduced, start planning for review
  • - when spec is solid but not a final spec - primarily want to nail down opcode/CSR assignment and have a solid draft spec (but not a final spec ready for official Arch Review)
  • Also, to remind people of what gets reviewed (as is appropriate for a given extension), see the following list.  In addition to the extension spec, please submit information about the PoCs and about utility/efficiency (although we don't need all the gory detail - a paragraph or so for each can be fine).  For items considered to not be consequential, a sentence or so explaining why should suffice.
    • Consistency with the RISC-V architecture and philosophy
    • Documentation clarity and completeness
      • Including proper distinction between normative and non-normative text
    • Motivation and rationale for the features, instructions, and CSRs
    • Utility and efficiency (relative to existing architectural features and mechanisms)
      • Is there enough value or benefit to justify the cost of implementation
      • Is the cost in terms of area, timing, and complexity reasonable
    • Proof of Concept (PoC)
      • Software PoC to ensure feature completeness and appropriateness for intended use cases
      • Hardware PoC to demonstrate reasonable implementability
    • Inappropriate references to protected IP (i.e. covered by patents, copyright, etc.)

Architecture Tests

  • Deterministic Test plan for the fast-interrupt is available.  Discussion on-going on how to add async/undeterministic testing of interrupts.
  • YAML config needs to be created.  See info here.
  • Discussion in Arch tests group to add automation (docker?) to validate check-in so that arch-test-suite is run against sail, spike, gcc/toolchain, with versions used recorded.  So sail and spike will need to work for CLIC before CLIC tests can be added to riscv-config github.

Compilers / Toolchains

GCC and Binutils

  • No new instructions are added.  Needs to be aware CSR names?  Need to choose arch string. Given that the key CSRs are in M-mode, it should probably be named something like "Smclic"


  • No new instructions are added.  Needs to be aware of CSR names? 


Though all listed under "simulators", these are actually a collection of formal model / virtual machine / architectural simulators / DV simulators etc.



  • TBD



Proof-of-Concept implementations


Project NameBase ArchitectureLevel of implementationNotes
area-optimized coreRV32/64

RTL simulation, FPGA Implementation, Synthesis

closed / commercial source
high-performance coreRV32RTL simulation, FPGA Implementation, Synthesisclosed / commercial source
microcontroller-class coreRV32IMAFCRTL, fully synthesizableApache License, Version 2.0
E2/S2 seriesRV32/64RTL, fully synthesizable
N22RV32RTL, fully synthesizable
BM-310/BI-651RV32/64RTL, fully synthesizable
n200/n900/nx900/ux900RV32/64RTL, fully synthesizable  (ECLIC)
R9A02G021RV32samples availableR9A02G021 Datasheet (



ABI Extensions (no new ABI required)

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