Major items on Freeze Checklist:
Saravana introduction. will be working on interrupts and SAIL. From networking background. Coming up to speed on SAIL model. Went through cookbook model. Starting with PLIC. PLIC is non-ISA. interrupt registers PLIC is almost completely MMIO addresses. wires from PLIC into interrupt registers. That I/f is sort of architectural. hook up pseudo event generator to wiggle the wires. if hook up PLIC have to connect to PLIC.
From a hart perspective there are a lot of interrupt wires coming in. how do they get there. incoming write addr turns into wiggling a wire.
Event generator relative to retired count of a hart. Assert the wire 5 instruction retires from now. As independent from implementation as possible. instruction retires are relatively deterministic.
SAIL status – 1 more pull request for vector. do have backlog. 7 or 8 prs that are pending. some PRs may affect the same file. instruction extension usually just a separate file. CLIC will add CSRs and is more complicated (touch at least 3 files). RNMI. PRs priority things that are ratified.
If there is a PR for ACT should have been tested and compared to Spike. riscv-non-isa/riscv-arch-test (github.com)
Ovpsim may be a good alternative to spike with initial development while spike is being updated. have to do in environment that generates interrupts.
Regression testing – interaction with CLINT.
Would CLIC get its own folder under riscv-arch-test/riscv-test-suite/rv32i?
In one place but say execute if RV32I or RV64I or don’t run test.
Test plan – need to write something that stimulates clic sources, turns into wires.
ACT – read/understood/implemented the spec. not DV coverage (lots of combinations). but do want some cross-coverage.
riscv-software-src/riscv-config: RISC-V Configuration Validator (github.com)
Schema_isa.yaml - gives allowed configuration on risc-v and allowed values. WARL fields give allowed ranges. 10k lines in file.
Examples/rivc32i_isa.yaml is compared against schema_isa.yaml to see if it is allowed.
When add new CSRs, add PR to add to schema_isa.yaml and then will be checked against example implementation.
Schemas/schema_platforml.yaml - memory mapped registers (like clicintctl, etc.)
Run python scripts that look at your implementation and see if it is valid. e.g., if have d then have f- extenstion, etc. checks if WARL field is valid.
Write anything, read legal. mapping from what is illegal to what is legal. mapping is arbitrary. so prefer (easiest) if implementers implement when write something illegal, don’t write. that works easiest for describing in this file.
Though all listed under "simulators", these are actually a collection of formal model / virtual machine / architectural simulators / DV simulators etc.
|Project Name||Base Architecture||Level of implementation||Notes|
RTL simulation, FPGA Implementation, Synthesis
|closed / commercial source https://www.seagate.com/innovation/risc-v/|
|high-performance core||RV32||RTL simulation, FPGA Implementation, Synthesis||closed / commercial source https://www.seagate.com/innovation/risc-v/|
|microcontroller-class core||RV32IMAFC||RTL, fully synthesizable||Apache License, Version 2.0 https://github.com/T-head-Semi/opene906/blob/main/doc/opene906_datasheet.pdf|
|E2/S2 series||RV32/64||RTL, fully synthesizable||https://www.sifive.com/core-designer|
|N22||RV32||RTL, fully synthesizable||http://www.andestech.com/en/products-solutions/andescore-processors/riscv-n22/|
|BM-310/BI-651||RV32/64||RTL, fully synthesizable||https://cloudbear.ru/bm_310.html https://cloudbear.ru/bi_651.html|
|n200/n900/nx900/ux900||RV32/64||RTL, fully synthesizable (ECLIC)||https://www.nucleisys.com/product.php?site=n200 https://www.nucleisys.com/product.php?site=n900|