RISC-V International

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Comment: added sifive and andes products to proof-of-concept table

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Project NameBase ArchitectureLevel of implementationNotes
area-optimized coreRV32/64

RTL simulation, FPGA Implementation, Synthesis

closed / commercial source   https://www.seagate.com/innovation/risc-v/
high-performance coreRV32RTL simulation, FPGA Implementation, Synthesisclosed / commercial source   https://www.seagate.com/innovation/risc-v/
microcontroller-class coreRV32IMAFCRTL, fully synthesizableApache License, Version 2.0 https://github.com/T-head-Semi/opene906/blob/main/doc/opene906_datasheet.pdf
E2/S2 seriesRV32/64RTL, fully synthesizablehttps://www.sifive.com/core-designer
N22RV32RTL, fully synthesizablehttp://www.andestech.com/en/products-solutions/andescore-processors/riscv-n22/








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