RISC-V International
Page History
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| Project Name | Base Architecture | Level of implementation | Notes |
|---|---|---|---|
| area-optimized core | RV32/64 | RTL simulation, FPGA Implementation, Synthesis | closed / commercial source https://www.seagate.com/innovation/risc-v/ |
| high-performance core | RV32 | RTL simulation, FPGA Implementation, Synthesis | closed / commercial source https://www.seagate.com/innovation/risc-v/ |
| microcontroller-class core | RV32IMAFC | RTL, fully synthesizable | Apache License, Version 2.0 https://github.com/T-head-Semi/opene906/blob/main/doc/opene906_datasheet.pdf |
| E2/S2 series | RV32/64 | RTL, fully synthesizable | https://www.sifive.com/core-designer |
| N22 | RV32 | RTL, fully synthesizable | http://www.andestech.com/en/products-solutions/andescore-processors/riscv-n22/ |
| BM-310/BI-651 | RV32/64 | RTL, fully synthesizable | https://cloudbear.ru/bm_310.html https://cloudbear.ru/bi_651.html |
| n200/n900/nx900/ux900 | RV32/64 | RTL, fully synthesizable (ECLIC) | https://www.nucleisys.com/product.php?site=n200 https://www.nucleisys.com/product.php?site=n900 |
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