RISC-V International
Page History
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In-process Non-ISA Specification Status
Ratification Package
| Task group approved by TSC date | Specification State**** | Committee (Owner) | Task Group | Plan Milestone Target Date | Freeze Milestone Target Date | Ratification Milestone Target Date | Plan Milestone next step* | Freeze Milestone next step** | Ratification *** | Last Updated | Notes |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Plan Complete | Security HC (Ravi Sahita, Guerney Hunt) | AP-TEE | Q1'23 | Q2'23 | Q3'23 | review by chairs | |||||
| 2020 | New | ISA Infrastructure HC | Architecture Test SIG?? | review by chairs |
| Need to identify the track of approvals and discussion given it was started back in 2018. | ||||||
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| Plan Complete | SOC Infrastructure HC (Ved Shanbhogue, Perrine Peresse) | IOMMU | 2Q'22 | Q1'23 | complete | AR approval | ||||||||||||
| New | Security HC | IOPMP | Q1'23 | Q3'23 | Q4'23 | review by chairs | |||||||||||
| New | SOC Infrastructure HC (Robert Chyla) | Nexus Trace | Q1'23 | Q1'23 | Q2'23 | review by chairs | Plan milestone review | ||||||||||
OS-A SEE *Missing Artifacts |
| New | Privileged Software HC (Aaron Durbin) | OS-A SEE | Q2'23 | build plan | ||||||||||||
Platform Runtime Services *Missing Artifacts |
| New | Privileged Software HC (Atish Patra & Sunil VL) | Platform Runtime Services | ||||||||||||||
| 2020 | TSC Approved | Privileged Software HC (Abner Chang) | Q3'22 | Q4'22 | complete | complete | BoD approval | No waivers | ||||||||||
| New | SOC Infrastructure HC (Dimitris Gizopoulos, Cameron McNairy) | RAS Terms and Defintions | build plan | ||||||||||||||
| New | Applications & Tools HC | RISC-V Vector C Intrinsics | build plan | ||||||||||||||
| New | Security HC (Xueyang Terry Wang, Suresh Sugumar) | Security Model | plan review by chairs | ||||||||||||||
| New | Privileged Software HC (Irma Flores-Mendoza | Unified Discovery | Q3'22 | plan review by chairs |
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Status Key
The following steps and associated next sequential steps for the milestones listed in the tables above may be parallelized at times, but are most simply thought of as a sequential set. All previous steps are done. For more details on each step, see the RISC-V Lifecycle Guide section on "Specification Lifecycle" and it's specific subsections for each milestone, including step-by-step descriptions.
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