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This page contains the single list of of all ratified technical publications.

ISA Specifications

These are the current, published versions of the ISA specifications.  Prior published versions and the original ratification specifications for included extensions may be found on the RISC-V Technical Specifications Archive page.

Note: Recently ratified extensions, but not yet included in the full specifications above, can be found on the RISC-V Ratified Extensions page.

Non-ISA Specifications

These are the current, published versions of the non-ISA specifications.  Prior published versions may be found on the RISC-V Technical Specifications Archive page.

Specification nameVersionFirst PublishedLast UpdatedDescriptionRISC-V CommunitySource Repository
Efficient Trace for RISC-V2.0.3June 2022April 2024Specifies the signals between the RISC-V core and the encoder, compressed branch trace algorithm, and the packet format used to encapsulate the compressed branch trace information to implement processor tracing.SOC Infrastructure Horizontal Committeeriscv-non-isa/tech-trace-spec
RISC-V ABIs Specification1.0November 2022
Provides the processor-specific application binary interface document for RISC-VApplication & Tools Horizontal Committeeriscv-non-isa/riscv-elf-psabi-doc
RISC-V Advanced Interrupt Architecture1.0June 2023
Describes an Advanced Interrupt Architecture for RISC-V systems.Privileged Software Horizontal Committeeriscv/riscv-aia
RISC-V External Debug Support0.13.2March 2019
Outlines a standard architecture for external debug support on RISC-V platforms.SOC Infrastructure Horizontal Committeeriscv/tech-debug-spec
RISC-V Functional Fixed Hardware
Specification
1.0.0January 2024
Provides additional system specification for RISC-V systems which use Advanced Configuration and Power Interface (ACPI), specifically for some ACPI object fields of type “Resource Descriptor”.Privileged Software Horizontal Committeeriscv-non-isa/riscv-acpi-ffh
RISC-V IOMMU Architecture
Specification
1.0.0June 2023
Describes an Input-Output Memory Management Unit (IOMMU) that connects direct-memory-access-capable Input/Output (I/O) devices to system memory.SOC Infrastructure Horizontal Committee

riscv-non-isa/riscv-iommu

RISC-V Platform-Level Interrupt Controller Specification1.0.0February 2023
Delineates the operational parameters for a platform-level interrupt controller on RISC-V.Privileged Software Horizontal Committeeriscv/riscv-plic-specRISC-V Supervisor Binary Interface Specification1.0.0May 2022Describes the RISC-V Supervisor Binary Interface, known from here on as SBI which enables supervisor-mode (S-mode or VS-mode) software to be portable across all RISC-V implementations by defining an abstraction for platform (or hypervisor) specific functionality.Privileged Software Horizontal Committeeriscv-non-isa/riscv-sbi-doc
RISC-V Supervisor Binary Interface Specification2.0.0January 2024
Second publication of the RISC-V Supervisor Binary Interface specification.  It added a debug console, system suspend, nested acceleration, steal-time accounting, PMU snapshot, and various error codes; relaxed counter width requirements on PMU firmware counters; reserved space for firmware events;  and clarified several extensions.Privileged Software Horizontal Committeeriscv-non-isa/riscv-sbi-doc
RISC-V UEFI Protocol Specification1.0.0May 2022
Details all new UEFI protocols required only for RISC-V platforms.Privileged Software Horizontal Committeeriscv-non-isa/riscv-uefi

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