Efficient Trace for RISC-V

Specifies the signals between the RISC-V core and the encoder, compressed branch trace algorithm, and the packet format used to encapsulate the compressed branch trace information to implement processor tracing.

RISC-V ABIs Specification

Provides the processor-specific application binary interface document for RISC-V.

RISC-V Advanced Interrupt Architecture

Describes an Advanced Interrupt Architecture for RISC-V systems.

RISC-V Capacity and Bandwidth QoS Register Interface

Specifies:

1. QoS identifiers to identify workloads that originate requests to the shared resources.
2. Access-type identifiers to accompany request to access a shared resource to allow differentiated treatment of each access-type.
3. Register interface for capacity allocation in controllers such as shared caches, directories, etc.
4. Register interface for capacity usage monitoring.
5. Register interface for bandwidth allocation in controllers such as interconnect and memory
   controllers.
6. Register interface for bandwidth usage monitoring.

RISC-V External Debug Support

Outlines a standard architecture for external debug support on RISC-V platforms.

RISC-V Functional Fixed Hardware Specification

Provides additional system specification for RISC-V systems which use Advanced Configuration and Power Interface (ACPI), specifically for some ACPI object fields of type “Resource Descriptor”.

RISC-V IOMMU Architecture Specification  

Describes an Input-Output Memory Management Unit (IOMMU) that connects direct-memory-access-capable Input/Output (I/O) devices to system memory.

riscv-non-isa/riscv-iommu

RISC-V Platform-Level Interrupt Controller Specification

Delineates the operational parameters for a platform-level interrupt controller on RISC-V.

RISC-V RERI Architecture Specification

Augments Reliability, Availability, and Serviceability (RAS) features in the SoC with a standard mechanism for reporting errors by means of a memory-mapped register interface to enable error reporting. Additionally, this specification supports software-initiated error logging, reporting, and testing of RAS handlers. Lastly, this specification provides maximal flexibility to implement error handling and coexists with RAS frameworks defined by other standards such as PCIe and CXL.

RISC-V Supervisor Binary Interface Specification

Second publication of the RISC-V Supervisor Binary Interface specification.  It added a debug console, system suspend, nested acceleration, steal-time accounting, PMU snapshot, and various error codes; relaxed counter width requirements on PMU firmware counters; reserved space for firmware events;  and clarified several extensions.

RISC-V UEFI Protocol Specification

Details all new UEFI protocols required only for RISC-V platforms.

Unformatted Trace & Diagnostic Data Packet Encapsulation for RISC-V

Defines an encapsulation format suitable for use with a variety of transport mechanisms, including but not limited to AMBA Advanced Trace Bus (ATB) and Siemens' Messaging Infrastructure.