This page contains the single list of of all ratified technical publications.

ISA Specifications

Specification nameVersionPublish DateRISC-V CommunitySource Repository
The RISC-V Instruction Set Manual
Volume I: Unprivileged ISA 		20191213Dec. 2019Unprivileged Horizontal Committeeriscv/riscv-isa-manual
The RISC-V Instruction Set Manual
Volume II: Privileged Architecture 		20211203Dec. 2021Privileged Horizontal Committeeriscv/riscv-isa-manual

Note: Recently ratified extensions, but yet included in the full specifications above, can be found on the RISC-V Recently Ratified Extensions page.

Non-ISA Specifications

Specification nameVersionPublish DateDescriptionRISC-V CommunitySource Repository
Efficient Trace for RISC-V2.0June 2022Specifies the signals between the RISC-V core and the encoder, compressed branch trace algorithm, and the packet format used to encapsulate the compressed branch trace information to implement processor tracing.SOC Infrastructure Horizontal Committeeriscv-non-isa/tech-trace-spec
RISC-V ABIs Specification1.0November 2022Provides the processor-specific application binary interface document for RISC-VApplication & Tools Horizontal Committeeriscv-non-isa/riscv-elf-psabi-doc
RISC-V Advanced Interrupt Architecture1.0June 2023Describes an Advanced Interrupt Architecture for RISC-V systems.Privileged Software Horizontal Committeeriscv/riscv-aia
RISC-V External Debug Support0.13.2March 2019Outlines a standard architecture for external debug support on RISC-V platforms.SOC Infrastructure Horizontal Committeeriscv/tech-debug-spec
RISC-V IOMMU Architecture
Specification		1.0.0June 2023Describes an Input-Output Memory Management Unit (IOMMU) that connects direct-memory-access-capable Input/Output (I/O) devices to system memory.SOC Infrastructure Horizontal Committee

riscv-non-isa/riscv-iommu

RISC-V Platform-Level Interrupt Controller Specification1.0.0February 2023Delineates the operational parameters for a platform-level interrupt controller on RISC-V.Privileged Software Horizontal Committeeriscv/riscv-plic-spec
RISC-V Supervisor Binary Interface Specification1.0.0May 2022Describes the RISC-V Supervisor Binary Interface, known from here on as SBI which enables supervisor-mode (S-mode or VS-mode) software to be portable across all RISC-V implementations by defining an abstraction for platform (or hypervisor) specific functionality.Privileged Software Horizontal Committeeriscv-non-isa/riscv-sbi-doc
RISC-V UEFI Protocol Specification1.0.0May 2022Details all new UEFI protocols required only for RISC-V platforms.Privileged Software Horizontal Committeeriscv-non-isa/riscv-uefi

Note: If you do not see a specification in the above table, visit the RISC-V GitHub riscv-non-isa organization to see a complete list of all specifications which have been developed or are presently under development.

Compatibility Test Framework

The RISC-V Architectural Compatibility Test Framework Version 3 (RISCOF version 1.X) is now available.

This framework compares two arbitrary models against each other using a reference signature (one of which should be a reference model) and automatically selects tests according to the model configuration.  Because the RISC-V ISA specification allows many architectural implementation choices, a tool (RISCV-CONFIG) has been created to describe implementation configurations.  The RISCOF Framework uses RISCV-CONFIG to select and configure tests.

The current test coverage includes RV[32|64]IMCFD_Zb*_zK*_Zmmul_Zicsr_Zifencei (where * means a lot of sub extensions).  Work continues to expand extensions supported and configurations covered.

More information can be found in the following locations


  • No labels

Copyright (c) 2022, RISC-V International