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This page contains the single list of of all ratified technical publications.

ISA Specifications

Note: Recently ratified extensions, but yet included in the full specifications above, can be found on the RISC-V Recently Ratified Extensions page.

Non-ISA Specifications

Specification nameVersionPublish DateDescriptionRISC-V CommunitySource Repository
Efficient Trace for RISC-V2.0June 2022Specifies the signals between the RISC-V core and the encoder, compressed branch trace algorithm, and the packet format used to encapsulate the compressed branch trace information to implement processor tracing.SOC Infrastructure Horizontal Committeeriscv-non-isa/tech-trace-spec
RISC-V ABIs Specification1.0November 2022Provides the processor-specific application binary interface document for RISC-VApplication & Tools Horizontal Committeeriscv-non-isa/riscv-elf-psabi-doc
RISC-V External Debug Support0.13.2March 2019Outlines a standard architecture for external debug support on RISC-V platforms.SOC Infrastructure Horizontal Committeeriscv/tech-debug-spec
RISC-V Platform-Level Interrupt Controller Specification1.0.0February 2023Delineates the operational parameters for a platform-level interrupt controller on RISC-V.Privileged Software Horizontal Committeeriscv/riscv-plic-spec
RISC-V Supervisor Binary Interface Specification1.0.0May 2022Describes the RISC-V Supervisor Binary Interface, known from here on as SBI which enables supervisor-mode (S-mode or VS-mode) software to be portable across all RISC-V implementations by defining an abstraction for platform (or hypervisor) specific functionality.Privileged Software Horizontal Committeeriscv-non-isa/riscv-sbi-doc
RISC-V UEFI Protocol Specification1.0.0May 2022Details all new UEFI protocols required only for RISC-V platforms.Privileged Software Horizontal Committeeriscv-non-isa/riscv-uefi

Note: If you do not see a specification in the above table, visit the RISC-V GitHub riscv-non-isa organization to see a complete list of all specifications which have been developed or are presently under development.

Compatibility Test Framework

The RISC-V Architectural Compatibility Test Framework Version 2 is now available. This framework compares arbitrary models against a reference signature, and currently covers RV[32|64]IMC unprivileged specifications only. Tests for the not-yet-ratified Crypto Scalar extension and RV32EMC extensions are also available.

Work on Version 3.0 framework (RISCOF) is underway which will compare two arbitrary models against each other (one of which should be a reference model), expand the configurations covered, and will automatically select tests according to the model configuration.

The RISC-V ISA specification allows many architectural implementation choices. A tool has been created to describe implementation configurations (RISCV-CONFIG) that the RISCOF Framework will use to select and configure tests.

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  1. This section needs many updates: 

    • "The RISC-V Architectural Compatibility Test Framework Version 2 is now available"
       should be updated to version 3 (or whatever riscof returns a a version #!)
    • remove "the not-yet-ratiified Crypto Scalar extension, and add "Zk*" to the "currently covers" list
    • "Work on" .. is underway which will conpare" should be replaced with "...compares"
    • The bullet item "Compatibility Test Framework v2.0" should be removed
    • "beta" should be removed from the Framework bullet item, and a link to the documentation should be added
    • The RISC-CONFIG should have a github link added