RISC-V International
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Note: Recently ratified extensions, but not yet included in the full specifications above, can be found on the RISC-V Ratified Extensions page.
Profiles
The These are the current, published versions of the Profiles specifications.
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These are the current, published versions of the non-ISA specifications. Prior published versions can be found on the RISC-V Technical Specifications Archive page.
| Specification name | Version | Published | Updated |
|---|
| RISC-V Community | Source Repository | |
|---|---|---|
Specifies the signals between the RISC-V core and the encoder, compressed branch trace algorithm, and the packet format used to encapsulate the compressed branch trace information to implement processor tracing. | 2.0.3 | June 2022 | April 2024 | SOC Infrastructure Horizontal Committee | riscv-non-isa/tech-trace-spec |
Provides the processor-specific application binary interface document for RISC-V. | 1.0 | November 2022 | Application & Tools Horizontal Committee | riscv-non-isa/riscv-elf-psabi-doc | |
Describes an Advanced Interrupt Architecture for RISC-V systems. | 1.0 | June 2023 | Privileged Software Horizontal Committee | riscv/riscv-aia | |
Outlines a standard architecture for external debug support on RISC-V platforms. | 0.13.2 | March 2019 | SOC Infrastructure Horizontal Committee | riscv/tech-debug-spec | |
Provides additional system specification for RISC-V systems which use Advanced Configuration and Power Interface (ACPI), specifically for some ACPI object fields of type “Resource Descriptor”. | 1.0.0 | January 2024 | Privileged Software Horizontal Committee | riscv-non-isa/riscv-acpi-ffh | |
Describes an Input-Output Memory Management Unit (IOMMU) that connects direct-memory-access-capable Input/Output (I/O) devices to system memory. | 1.0.0 | June 2023 | SOC Infrastructure Horizontal Committee | ||
Delineates the operational parameters for a platform-level interrupt controller on RISC-V. | 1.0.0 | February 2023 | Privileged Software Horizontal Committee | riscv/riscv-plic-spec | |
Second publication of the RISC-V Supervisor Binary Interface specification. It added a debug console, system suspend, nested acceleration, steal-time accounting, PMU snapshot, and various error codes; relaxed counter width requirements on PMU firmware counters; reserved space for firmware events; and clarified several extensions. | 2.0.0 | January 2024 | Privileged Software Horizontal Committee | riscv-non-isa/riscv-sbi-doc | |
Details all new UEFI protocols required only for RISC-V platforms. | 1.0.0 | May 2022 | Privileged Software Horizontal Committee | riscv-non-isa/riscv-uefi |
Note: If you do not see a specification in the above table, visit the RISC-V GitHub riscv-non-isa organization to see a complete list of all specifications which have been developed or are presently under development.
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