RISC-V International
Page History
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| Specification | Version | Published | Updated | RISC-V Community | Source Repository |
|---|---|---|---|---|---|
Specifies the signals between the RISC-V core and the encoder, compressed branch trace algorithm, and the packet format used to encapsulate the compressed branch trace information to implement processor tracing. | 2.0.3 | June 2022 | April 2024 | SOC Infrastructure Horizontal Committee | riscv-non-isa/tech-trace-spec |
Provides the processor-specific application binary interface document for RISC-V. | 1.0 | November 2022 | Application & Tools Horizontal Committee | riscv-non-isa/riscv-elf-psabi-doc | |
RISC-V Advanced Interrupt Architecture Describes an Advanced Interrupt Architecture for RISC-V systems. | 1.0 | June 2023 | Privileged Software Horizontal Committee | riscv/riscv-aia | |
Outlines a standard architecture for external debug support on RISC-V platforms. | 0.13.2 | March 2019 | SOC Infrastructure Horizontal Committee | riscv/tech-debug-spec | |
RISC-V Functional Fixed Hardware Provides additional system specification for RISC-V systems which use Advanced Configuration and Power Interface (ACPI), specifically for some ACPI object fields of type “Resource Descriptor”. | 1.0.0 | January 2024 | Privileged Software Horizontal Committee | riscv-non-isa/riscv-acpi-ffh | |
RISC-V IOMMU Architecture Describes an Input-Output Memory Management Unit (IOMMU) that connects direct-memory-access-capable Input/Output (I/O) devices to system memory. | 1.0.0 | June 2023 | SOC Infrastructure Horizontal Committee | ||
RISC-V Platform-Level Interrupt Controller Specification Delineates the operational parameters for a platform-level interrupt controller on RISC-V. | 1.0.0 | February 2023 | Privileged Software Horizontal Committee | riscv/riscv-plic-spec | |
RISC-V RERI Architecture Specification Augments Reliability, Availability, and Serviceability (RAS) features in the SoC with a standard mechanism for reporting errors by means of a memory-mapped register interface to enable error reporting. Additionally, this specification supports software-initiated error logging, reporting, and testing of RAS handlers. Lastly, this specification provides maximal flexibility to implement error handling and coexists with RAS frameworks defined by other standards such as PCIe and CXL. | 1.0 | May 2024 | SOC Infrastructure Horizontal Committee | riscv-non-isa/riscv-ras-eri | |
RISC-V Supervisor Binary Interface Specification Second publication of the RISC-V Supervisor Binary Interface specification. It added a debug console, system suspend, nested acceleration, steal-time accounting, PMU snapshot, and various error codes; relaxed counter width requirements on PMU firmware counters; reserved space for firmware events; and clarified several extensions. | 2.0.0 | January 2024 | Privileged Software Horizontal Committee | riscv-non-isa/riscv-sbi-doc | |
RISC-V UEFI Protocol Specification Details all new UEFI protocols required only for RISC-V platforms. | 1.0.0 | May 2022 | Privileged Software Horizontal Committee | riscv-non-isa/riscv-uefi |
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