RISC-V International
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These are the current, published versions of the ISA specifications. Prior published versions and the original ratification specifications for included extensions may can be found on the RISC-V Technical Specifications Archive page.
| Specification name | VersionPublish Date | Published | RISC-V Community | Source Repository |
|---|---|---|---|---|
| The RISC-V Instruction Set Manual Volume I: Unprivileged ISA | 20240411 | May 2024 | Unprivileged Horizontal Committee | riscv/riscv-isa-manual |
| The RISC-V Instruction Set Manual Volume II: Privileged Architecture | 20240411 | May 2024 | Privileged Horizontal Committee | riscv/riscv-isa-manual |
Note: Recently ratified extensions, but not yet included in the full specifications above, can be found on the RISC-V V Ratified Extensions page.
Profiles
These are the current, published versions of the Profiles specifications.
| Specification name | Version | Published | Profile(s) | RISC-V Community | Source Repository |
|---|---|---|---|---|---|
| RISC-V Profiles | 1.0 | March 2023 | RVA20, RVI20, RVA22 | Profiles SIG | riscv/riscv-profiles |
Non-ISA Specifications
These are the current, published versions of the non-ISA specifications. Prior published versions may can be found on the RISC-V Technical Specifications Archive page.
| Specification |
|---|
| Version |
|---|
| Published |
|---|
| Updated |
|---|
| RISC-V Community | Source Repository | |
|---|---|---|
Specifies the signals between the RISC-V core and the encoder, compressed branch trace algorithm, and the packet format used to encapsulate the compressed branch trace information to implement processor tracing. | 2.0.3 | June 2022 | April 2024 | SOC Infrastructure Horizontal Committee | riscv-non-isa/tech-trace-spec |
Provides the processor-specific application binary interface document for RISC-V. | 1.0 | November 2022 | Application & Tools Horizontal Committee | riscv-non-isa/riscv-elf-psabi-doc | |
Describes an Advanced Interrupt Architecture for RISC-V systems. | 1.0 | June 2023 | Privileged Software Horizontal Committee | riscv/riscv-aia | |
Capacity and Bandwidth QoS Register Interface Specifies:
| 1.0 | June 2024 | SOC Infrastructure Horizontal Committee | riscv-non-isa/riscv-cbqri | |
Outlines a standard architecture for external debug support on RISC-V platforms. | 0.13.2 | March 2019 | SOC Infrastructure Horizontal Committee | riscv/tech-debug-spec | |
Specification
Provides additional system specification for RISC-V systems which use Advanced Configuration and Power Interface (ACPI), specifically for some ACPI object fields of type “Resource Descriptor”. | 1.0.0 | January 2024 | Privileged Software Horizontal Committee | riscv-non-isa/riscv-acpi-ffh | |
Describes an Input-Output Memory Management Unit (IOMMU) that connects direct-memory-access-capable Input/Output (I/O) devices to system memory. | 1.0.1 | June 2023 | September 2024 | SOC Infrastructure Horizontal Committee | |
Delineates the operational parameters for a platform-level interrupt controller on RISC-V. | 1.0.0 | February 2023 | Privileged Software Horizontal Committee | riscv/riscv-plic-spec | |
RERI Architecture Specification Augments Reliability, Availability, and Serviceability (RAS) features in the SoC with a standard mechanism for reporting errors by means of a memory-mapped register interface to enable error reporting. Additionally, this specification supports software-initiated error logging, reporting, and testing of RAS handlers. Lastly, this specification provides maximal flexibility to implement error handling and coexists with RAS frameworks defined by other standards such as PCIe and CXL. | 1.0 | May 2024 | SOC Infrastructure Horizontal Committee | riscv-non-isa/riscv-ras-eri | |
Second publication of the RISC-V Supervisor Binary Interface specification. It added a debug console, system suspend, nested acceleration, steal-time accounting, PMU snapshot, and various error codes; relaxed counter width requirements on PMU firmware counters; reserved space for firmware events; and clarified several extensions. | 2.0.0 | January 2024 | Privileged Software Horizontal Committee | riscv-non-isa/riscv-sbi-doc | |
Details all new UEFI protocols required only for RISC-V platforms. | 1.0.0 | May 2022 | Privileged Software Horizontal Committee | riscv-non-isa/riscv-uefi | |
Unformatted Trace & Diagnostic Data Packet Encapsulation for RISC-V Defines an encapsulation format suitable for use with a variety of transport mechanisms, including but not limited to AMBA Advanced Trace Bus (ATB) and Siemens' Messaging Infrastructure. | 1.0 | June 2024 | SOC Infrastructure Horizontal Committee | riscv-non-isa/e-trace-encap |
Note: If you do not see a specification in the above table, visit the RISC-V GitHub riscv-non-isa organization to see a complete list of all specifications which have been developed or are presently under development.
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