Page History

This page gives an overview of the extension and feature support in the RISC-V SW ecosystem.

Overview

• This page only tracks ratified extensions and features that are specified by groups (TGs, HCs) of RISC-V International.
• The extensions and features are grouped by their specification's state (published, ratified, frozen).
• Published (official) specifications can be found here: https://riscv.org/technical/specifications/
• The main repository of the ISA specifications is: https://github.com/riscv/riscv-isa-manual

Certain extensions are generated by individual TGs.

An overview of the current status of unratified extensions can be found here: Architecture Review

• The following wiki page lists all recently ratified extensions, that are not merged into the ISA specification yet: Ratified Extensions
• The Specification Status lists the specifications that are frozen or ready for ratification

Table description

The subsections below contain tables that summarize the current state of extensions and features. The following description helps to interpret the table cell's contents:

• upstream...SW support has been merged into the main development branch of the corresponding SW project
• staging branch...SW support lives in a staging branch and is not upstreamed
• PR...SW support exists in form of a pull request for upstream (in-review or waiting for ratification)
• n/a...not applicable, not relevant, or not required
• missing...currently no known implementation
• dev:X...feature is in development by X
• empty cells...unknown status (feel free to share your knowledge)

ISA extension naming conventions

This is just a summary of the naming convention as defined in the unpriv specification.

ISA extension description example: RV64I1p0M1p0A1p0F1p0D1p0 or RV32I2_M2_A2 (P extension requires underscore!)

Prefixes:

• Extensions with prefix Z...standard user-level
• Extensions with prefix X...non-standard user-level
• Extensions with prefix S...standard supervisor-level
• Extensions with prefix SX...non-standard supervisor-level

Published specifications (20191213)

• The RISC-V Instruction Set Manual, Volume I: User-Level ISA, Document Version 20191213
• The RISC-V Instruction Set Manual, Volume II: Privileged Architecture, Document
  Version 20190608-Priv-MSU-Ratified

The table below lists the status of the extensions and features of above listed published extensions.

Unpublished ratified extensions

Extensions and features in the table below are ratified, but not published in a consolidated RISC-V ISA specification document.

upstream...SW support has been merged into the main development branch of the corresponding SW project
staging branch...SW support lives in a staging branch and is not upstreamed
PR...SW support exists in form of a pull request for upstream (in-review or waiting for ratification)
n/a...not applicable, not relevant, or not required
missing...currently no known implementation
dev:X...feature is in development by X
empty cells...unknown status (feel free to share your knowledge)

ISA extension naming conventions

E.g.: RV64I1p0M1p0A1p0F1p0D1p0 or RV32I2_M2_A2 (P extension requires underscore!)

The complete ISA extension naming convention can be found in the unpriv specification.

...

Specifications that are at least frozen

Extensions and features in the table below are either frozen or ready-for-ratification.

Specifications that are at least stable

Note, that this section only lists specifications that are planned to be released in the near future, but are not frozen yet.

Specifications that are not stable

Note that this section only exists for historical purposes and the table below is not considered complete. Further, there are no attempts to track the SW support of unstable features here. 

Gaps

• Vector Extension Intrinsics (specification exists, but not frozen)
• Vector Calling Convention (specification exists, but not frozen)
• Scalar Crypto Intrinsics