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This page gives an overview of the extension and feature support in the RISC-V SW ecosystem.

Published specifications can be found here: https://riscv.org/technical/specifications/

The main repository of the ISA specifications is: https://github.com/riscv/riscv-isa-manual

Certain extensions are generated by individual TGs.

An overview of the current status of unratified extensions can be found here: Architecture Review

Latest specification

ExtensionRatified?SpikeQemuBinutilsGCCglibcnewlibLLVMOpenSBIFreeBSDLinuxGDB
Unpriv Spec 20191213RV32Iyupstreamupstreamupstreamupstreamupstreamupstreamupstreamupstreamnot supportedupstream
Unpriv Spec 20191213RV64Iyupstreamupstreamupstreamupstreamupstreamupstreamupstreamupstreamupstreamupstream
Unpriv Spec 20191213Big-endian supportyupstream

upstream

not supported



Unpriv Spec 20191213M (Multiplication and Division) v2.0yupstreamupstreamupstreamupstreamn/an/aupstreamn/an/an/a
Unpriv Spec 20191213A (Atomic)yupstreamupstreamupstreamupstreamn/an/aupstreamupstream (atomics)upstream (atomics)upstream (atomics)
Unpriv Spec 20191213F (SP float)yupstreamupstream



upstream



Unpriv Spec 20191213D (DP float)yupstreamupstream



upstream



Unpriv Spec 20191213Q (QP float)y

upstream


not supported



Unpriv Spec 20191213RVWMOyupstream (emulation is seq. consistent)upstream (emulation is seq. consistent)n/an/an/an/an/aupstream (barriers and locks)upstream (barriers and locks)upstream (barriers and locks), but needs optimization
psABIABIs (ILP32, ILP32E, ILP32F, ILP32D, LP64, LP64f, LP64D, LP64Q)


ilp32, ilp32f, ilp32d, ilp32q, ilp32e, lp64, lp64f, lp64d, lp64qilp32, ilp32f, ilp32d, ilp32e, lp64, lp64f, lp64dilp32, ilp32d, lp64, lp64dilp32, ilp32f, ilp32d, ilp32e, lp64, lp64f, lp64dilp32, ilp32d, lp64, lp64dn/alp64, lp64dn/a
Unpriv Spec 20191213C (compressed) v2.0yupstreamupstreamupstreamupstreamn/an/aupstream
upstream


Zifencei v2.0yupstreamupstreamupstream


not supported
upstreamupstream

Zihintpause v1.0


upstream


not supported




Zicsr v2.0yupstreamupstreamupstream


not supported
upstreamupstream

Counters v2.0nupstreamupstream
n/an/an/aupstreamupstream
upstream

Machine ISA v1.11 (CSRs, ECALL, EBREAK, MRET/SRET/URET, WFI, Reset, NMIs, PMAs, PMP)yupstreamupstream





n/an/a

Supervisor ISA v1.11 (CSRs, SFENCE.VMA, Sv32/Sv39/Sv48)yupstreamupstream




n/a



B (bitmanip) v0.92 (Zba, Zbb, Zbc, Zbe, Zbf, Zbk, Zbp, Zbr, Zbs)n

Mailpatch (Zba, Zbb, Zbs, Zbp)

PRdev branch

upstream (experimental)




K (scalar crypto)n

PRPR

MC layer PR LLVM Intrinsic PR




P (SIMD) v0.9.4nupstream (but v0.9.2!)Mailpatch (v0.9.4)PRPR

PR




V (vector) v0.10, Vector Extension Intrinsics, Vector Calling Conventionnupstreamupstream (but v0.7.1)



upstream (experimental,FP16 ABI not settled)




Ztso v0.1n





not supported




Zam v0.1n





not supported




H (hypervisor) v0.6.1nupstreamupstreamdev branchn/an/an/a
upstream
KVM patches on LKML

Zmmul v0.1 (subset of M)












J (JIT/Java)












TEE












Snavpotn











Zfinxnstaging branchstaging branchstaging branchstaging-branch

PR




Z*inx (with new ABIs: ILP32X/LP64X)


dev: PLCTdev: PLCT







Zfh






upstream




SV57












Zce


dev: PLCTdev: PLCT

dev branch




CMO / Zicmobasen










upstream...SW support has been merged into the main development branch of the corresponding SW project
staging branch...SW support lives in a staging branch and is not upstreamed
PR...SW support exists in form of a pull request for upstream (in-review or waiting for ratification)
n/a...not applicable, not relevant, or not required
missing...currently no known implementation
dev:X...feature is in development by X
empty cells...unknown status (feel free to share your knowledge)

ISA extension naming conventions

E.g.: RV64I1p0M1p0A1p0F1p0D1p0 or RV32I2_M2_A2 (P extension requires underscore!)

The complete ISA extension naming convention can be found in the unpriv specification.

Extensions with prefix Z...standard user-level
Extensions with prefix X...non-standard user-level
Extensions with prefix S...standard supervisor-level
Extensions with prefix SX...non-standard supervisor-level

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