RISC-V International
Page History
...
Note: Recently ratified extensions, but not yet included in the full specifications above, can be found on the RISC-V Recently Ratified Extensions page.
Non-ISA Specifications
| Specification name | Version | Publish Date | Description | RISC-V Community | Source Repository |
|---|---|---|---|---|---|
| Efficient Trace for RISC-V | 2.0.12 | June 2022 | Specifies the signals between the RISC-V core and the encoder, compressed branch trace algorithm, and the packet format used to encapsulate the compressed branch trace information to implement processor tracing. | SOC Infrastructure Horizontal Committee | riscv-non-isa/tech-trace-spec |
| RISC-V ABIs Specification | 1.0 | November 2022 | Provides the processor-specific application binary interface document for RISC-V | Application & Tools Horizontal Committee | riscv-non-isa/riscv-elf-psabi-doc |
| RISC-V Advanced Interrupt Architecture | 1.0 | June 2023 | Describes an Advanced Interrupt Architecture for RISC-V systems. | Privileged Software Horizontal Committee | riscv/riscv-aia |
| RISC-V External Debug Support | 0.13.2 | March 2019 | Outlines a standard architecture for external debug support on RISC-V platforms. | SOC Infrastructure Horizontal Committee | riscv/tech-debug-spec |
| RISC-V Functional Fixed Hardware Specification | 1.0.0 | January 2024 | Provides additional system specification for RISC-V systems which use Advanced Configuration and Power Interface (ACPI), specifically for some ACPI object fields of type “Resource Descriptor”. | Privileged Software Horizontal Committee | riscv-non-isa/riscv-acpi-ffh |
| RISC-V IOMMU Architecture Specification | 1.0.0 | June 2023 | Describes an Input-Output Memory Management Unit (IOMMU) that connects direct-memory-access-capable Input/Output (I/O) devices to system memory. | SOC Infrastructure Horizontal Committee | |
| RISC-V Platform-Level Interrupt Controller Specification | 1.0.0 | February 2023 | Delineates the operational parameters for a platform-level interrupt controller on RISC-V. | Privileged Software Horizontal Committee | riscv/riscv-plic-spec |
| RISC-V Supervisor Binary Interface Specification | 1.0.0 | May 2022 | Describes the RISC-V Supervisor Binary Interface, known from here on as SBI which enables supervisor-mode (S-mode or VS-mode) software to be portable across all RISC-V implementations by defining an abstraction for platform (or hypervisor) specific functionality. | Privileged Software Horizontal Committee | riscv-non-isa/riscv-sbi-doc |
| RISC-V Supervisor Binary Interface Specification | 2.0.0 | January 2024 | Second publication of the RISC-V Supervisor Binary Interface specification. It added a debug console, system suspend, nested acceleration, steal-time accounting, PMU snapshot, and various error codes; relaxed counter width requirements on PMU firmware counters; reserved space for firmware events; and clarified several extensions. | Privileged Software Horizontal Committee | riscv-non-isa/riscv-sbi-doc |
| RISC-V UEFI Protocol Specification | 1.0.0 | May 2022 | Details all new UEFI protocols required only for RISC-V platforms. | Privileged Software Horizontal Committee | riscv-non-isa/riscv-uefi |
...
Overview
Content Tools