You are viewing an old version of this page. View the current version.

Compare with Current View Page History

Version 1 Next »

This page gives an overview of the extension and feature support in the RISC-V SW ecosystem.

Published specifications can be found here: https://riscv.org/technical/specifications/

The main repository of the ISA specifications is: https://github.com/riscv/riscv-isa-manual

Certain extensions are generated by individual TGs.

An overview of the current status of unratified extensions can be found here: Opcode and State Review

Extension / featureRatified?SpikeQemuBinutilsGCCglibcnewlibLLVMOpenSBILinux
RV32I v2.1ymainlinemainlinemainlinemainlinemainlinemainlinemainline
mainline
RV64I v2.1ymainlinemainlinemainlinemainlinemainlinemainlinemainline
mainline
Big-endian supporty


mainline




RV32E v1.9n


mainline

not supported
not supported
Zifencei v2.0y






n/a
Zicsr v2.0y








M v2.0y








A v2.1ymainlinemainlinemainlinemainline (




F v2.2y








D v2.2y








C v2.0ymainlinemainline






Q v2.2y








RVWMO v2.0ymainline (emulation is seq. consistent)mainline (emulation is seq. consistent)






Ztso v0.1n








Zam v0.1n








Machine ISA v1.11 (CSRs, ECALL, EBREAK, MRET/SRET/URET, WFI, Reset, NMIs, PMAs, PMP)ymainlinemainline






Supervisor ISA v1.11 (CSRs, SFENCE.VMA, Sv32/Sv39/Sv48)ymainlinemainline






ABIs (ILP32, ILP32E, ILP32F, ILP32D, LP64, LP64f, LP64D, LP64Q)y

ilp32, ilp32d, lp64, lp64dilp32, ilp32d, lp64, lp64dilp32, ilp32d, lp64, lp64d
ilp32, ilp32d, lp64, lp64d

Experimental ABIs




















  • No labels

Copyright (c) 2024, RISC-V International