This page contains the list of all archived ratified technical specification version.  For the most recent versions of any specification, see the RISC-V Technical Specifications page.

NOTE: specifications not found on this page have only one version and thus are only available on the RISC-V Technical Specifications page.

Archive Contents

ISA Specifications

These sections contain previous, complete versions of the two ISA specification volumes.

The RISC-V Instruction Set Manual Volume I: Unprivileged ISA 

VersionPublish DateRISC-V CommunitySource Repository
20191213Dec. 2019Unprivileged Horizontal Committeeriscv/riscv-isa-manual

The RISC-V Instruction Set Manual Volume II: Privileged Architecture

VersionPublish DateRISC-V CommunitySource Repository
20211203Dec. 2021Privileged Horizontal Committeeriscv/riscv-isa-manual

ISA Ratification Specifications

This section contains the specifications which were independently ratified and subsequently have been pulled into the appropriate ISA volumes published on the RISC-V Technical Specifications page.

Specification nameRatifiedNew extension(s) or Profile(s)RISC-V CommunitySource
RISC-V Supervisor Counter DelegationMarch 2024Smcdeleg, SsccfgPrivileged Horizontal Committeeriscv-smcdeleg-ssccfg
May-Be-OperationsMarch 2024Zimop, ZcmopUnprivileged Horizontal Committee 
RISC-V Indirect CSR Access (Smcsrind/Sscsrind)February 2024Smcsrind, SscsrindPrivileged Horizontal Committeeriscv-indirect-csr-access
RISC-V Integer Conditional (Zicond) operations extensionNovember 2023ZicondUnprivileged Horizontal Committeeriscv-zicond
Hardware Updating of PTE A/D Bits (Svadu)November 2023SvaduPrivileged Horizontal Committeeriscv-svadu
RISC-V Cycle and Instret Privilege Mode Filtering (Smcntrpmf)November 2023SmcntrpmfPrivileged Horizontal Committeeriscv-smcntrpmf
Atomic Compare-and-Swap (CAS) Instructions (Zacas)November 2023ZacasUnprivileged Horizontal Committeeriscv-zacas
RISC-V Cryptography Extensions Volume II: Vector InstructionsSeptember 2023Zvbb, Zvbc, Zvkb, Zvkg, Zvkn, Zvknc, Zvkned, Zvkng, Zvknha, Zvknhb, Zvks, Zvksc, Zvksed, Zvksg, Zvksh, ZvktUnprivileged Horizontal Committeeriscv-crypto
"Zfa" Standard Extension for Additional Floating-Point InstructionsSeptember 2023ZfaUnprivileged Horizontal Committee 
RISC-V Advanced Interrupt ArchitectureJune 2023Smaia, SsaiaPrivileged Horizontal Committeeriscv-aia
“Zvfh/Zvfhmin:” Vector Extension for Half-Precision Floating-Point Arithmetic/Vector Extension for Minimal Half-
Precision Floating-Point Arithmetic
June 2023Zvfh, ZvfhminUnprivileged Horizontal Committee 
“Zihintntl” Non-Temporal Locality HintsMay 2023ZihintntlUnprivileged Horizontal Committee 
RISC-V Code Size ReductionApril 2023Zca, Zcb, Zcd, Zce, Zcf, Zcmp, ZcmtUnprivileged Horizontal Committeeriscv-code-size-reduction
"Zicntr" and "Zihpm" CountersMarch 2023Zicntr, ZihpmUnprivileged Horizontal Committee 
RV32E and RV64E Base Integer Instruction SetsJanuary 2023RV32E/RV64EUnprivileged Horizontal Committee
“Ztso” Standard Extension for Total Store OrderingJanuary 2023ZtsoUnprivileged Horizontal Committee
RISC-V Wait-on-Reservation-Set (Zawrs) extensionNovember 2022ZawrsUnprivileged Horizontal Committeeriscv-zawrs
Zmmul ExtensionJune 2022ZmmulUnprivileged Horizontal Committee
PMP Enhancements for memory access and execution prevention on Machine mode (Smepmp)November 2021SmepmpPrivileged Horizontal Committee
RISC-V Privileged Architecture 1.12November 2021Sm1p12, Ss1p12, Sv57, Hypervisor, Svinval, Svnapot, SvpbmtPrivileged Horizontal Committee
RISC-V Base Cache Management Operation ISA ExtensionsNovember 2021Zicbom, Zicbop, ZicbozUnprivileged Horizontal Committee
RISC-V Bit-Manipulation ISA-extensionsNovember 2021Zba, Zbb, Zbc, ZbsUnprivileged Horizontal Committeeriscv-bitmanip
RISC-V Count Overflow and Mode-Based Filtering ExtensionNovember 2021SscofpmfPrivileged Horizontal Committeeriscv-count-overflow
RISC-V Cryptography Extensions Volume I: Scalar & Entropy Source InstructionsNovember 2021Zbkb, Zbkc, Zbkx, Zknd, Zkne, Zknh, Zksed, Zksh, Zkn, Zks, Zkt, Zk, ZkrUnprivileged Horizontal Committeeriscv-crypto
RISC-V State Enable ExtensionNovember 2021SmstateenPrivileged Horizontal Committeeriscv-state-enable
RISC-V "stimecmp / vstimecmp" ExtensionNovember 2021SstcPrivileged Horizontal Committeeriscv-time-compare
RISC-V Vector ExtensionNovember 2021Zve32x, Zve32f, Zve64x, Zve64f, Zve64d, Zve, Zvl32b, Zvl64b, Zvl128b, Zvl256b, Zvl512b, Zvl1024b, Zvl, ZvUnprivileged Horizontal Committee 
"Zfh" and "Zfhmin" Standard Extensions for Half-Precision Floating-PointNovember 2021Zfh, ZfhminUnprivileged Horizontal Committee
"Zfinx", "Zdinx", "Zhinx", "Zhinxmin": Standard Extensions for Floating-Point in Integer RegistersNovember 2021Zfinx, Zdinx, Zhinx, ZhinxminUnprivileged Horizontal Committeeriscv-zfinx
“Zihintpause” Pause HintFebruary 2021ZihintpauseUnprivileged Horizontal Committee

Non-ISA Specifications

These sections contain previous versions of non-ISA specifications.

NOTE: specifications not found on this page have only one version and thus are only available on the RISC-V Technical Specifications page.

RISC-V Supervisor Binary Interface Specification

VersionPublishedDescriptionRISC-V CommunitySource
1.0.0May 2022Describes the RISC-V Supervisor Binary Interface, known from here on as SBI which enables supervisor-mode (S-mode or VS-mode) software to be portable across all RISC-V implementations by defining an abstraction for platform (or hypervisor) specific functionality.Privileged Software Horizontal Committeeriscv-non-isa/riscv-sbi-doc

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