Page History

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• Current  Definition-of-Done (wiki.riscv.org -> tech -> policies -> approved)   Status: kickoff  DoD status directory
• Next  Definition-of-Done Status: update DoD checklist Plan tab and send email to Chairs to transition from Kickoff to Plan  

Specification

• Latest Draft Fast Interrupt Specification (v0.9-draft-20210422)
  • updated adoc format to align with risc-v template, added revision history
• What's next:
  • 35 outstanding issues to be addressed.

Encoding/OpCode consistency review

• Need to propose new CLIC CSR Registers and addresses to be proposed

• What's next:   when outstanding issues are reduced, start planning for review

Architecture Tests

• Test plan for the fast-interrupt is available.
• YAML config needs to be created.  See examples here.

Compilers / Toolchains

GCC and Binutils

• N/A? No new instructions are added.  Needs to be aware CSR names?  Need to choose arch string like ziclic

LLVM

• N/A? No new instructions are added.  Needs to be aware of CSR names? 

Simulators

Though all listed under "simulators", these are actually a collection of formal model / virtual machine / architectural simulators / DV simulators etc.

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• TBD - Waiver until SAIL privilege model is completed?
• which github?  https://github.com/rems-project/sail-riscv or https://github.com/riscv/riscv-sail

Spike

• TBD

riscvOVPSimPlus

• Imperas Commercial Simulator
• Freeware versionSupport for:

QEMU

• QEMU implementation of CLIC-0.9 specification (Version 0.9-draft-20210217)

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