RISC-V International

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Status at a glance:

Specification

Encoding/OpCode consistency review

  • Need to propose new CLIC CSR Registers and addresses
  • What's next: when outstanding issues are reduced, start planning for review

Architecture Tests

  • Test plan for the fast-interrupt is available.
  • YAML config needs to be created.  See examples here.

Compilers / Toolchains

GCC and Binutils

  • No new instructions are added.  Needs to be aware CSR names?  Need to choose arch string like ziclic

LLVM

  • No new instructions are added.  Needs to be aware of CSR names? 

Simulators

Though all listed under "simulators", these are actually a collection of formal model / virtual machine / architectural simulators / DV simulators etc.

SAIL

Spike

  • TBD

riscvOVPSimPlus

QEMU

Proof-of-Concept implementations

Hardware

Project NameBase ArchitectureLevel of implementationNotes
area-optimized coreRV32/64

RTL simulation, FPGA Implementation, Synthesis

closed / commercial source   https://www.seagate.com/innovation/risc-v/
high-performance coreRV32RTL simulation, FPGA Implementation, Synthesisclosed / commercial source   https://www.seagate.com/innovation/risc-v/




















Software

Project/MaintainerDescription






ABI Extensions (no new ABI required)

  • Regular C function that save/restores all caller-save registers
  • Inline handler gcc interrupt attribute to always callee-save every register (save as you go)
  • EABI Task Group - improve interrupt latency by reducing the number of caller-save registers
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