Status at a glance:

• Current  Definition-of-Done (wiki.riscv.org -> tech -> policies -> approved)   Status: kickoff  DoD status directory
• Next  update DoD checklist Plan tab and send email to Chairs to transition from Kickoff to Plan  

Specification

• Latest Draft Fast Interrupt Specification (v0.9-draft-20210422)
  • updated adoc format to align with risc-v template, added revision history
• What's next:
  • 35 outstanding issues to be addressed.

Encoding/OpCode consistency review

• Need to propose new CLIC CSR Registers and addresses

• What's next: when outstanding issues are reduced, start planning for review

Architecture Tests

• Test plan for the fast-interrupt is available.
• YAML config needs to be created.  See examples here.

Compilers / Toolchains

GCC and Binutils

• No new instructions are added.  Needs to be aware CSR names?  Need to choose arch string like ziclic

LLVM

• No new instructions are added.  Needs to be aware of CSR names? 

Simulators

Though all listed under "simulators", these are actually a collection of formal model / virtual machine / architectural simulators / DV simulators etc.

SAIL

• TBD - Waiver until SAIL privilege model is completed?
• which github?  https://github.com/rems-project/sail-riscv or https://github.com/riscv/riscv-sail

Spike

• TBD

riscvOVPSimPlus

• Imperas Commercial Simulator
• Freeware version

QEMU

• QEMU implementation of CLIC-0.9 specification (Version 0.9-draft-20210217)

Proof-of-Concept implementations

Hardware

Software

ABI Extensions (no new ABI required)

• Regular C function that save/restores all caller-save registers
• Inline handler gcc interrupt attribute to always callee-save every register (save as you go)
• EABI Task Group - improve interrupt latency by reducing the number of caller-save registers