...

Lightweight instruction set extensions for RV32 and RV64 HARTs.  Proposed extensions:

• Defined Extensions fully defined in the Scalar Crypto Specification:  K, Zkn, Zks, Zkr, Zkne, Zknd, Zknh, Zkse, Zksd, Zksh
• Shared with the Bit-Manipulation Specification: Zkg, Zkb

Status by Topic:

Specification

• Stable
• What's next:
  • Needs translation into ASCIIDOC
  • Incorporate results of OpCode consistency review, once available

Every topic section:

Status (what's done, and not done), and What's next

links to GitHub, etc., as relevant to each of the topics here

links to PLTC and IIT Madras status pages, TBD

OpCode Encoding/OpCode consistency review

...

• OpCode and Consistency Review page
• What's next:  Respond to OpCode and Consistency Review comments, once available, and achieve consensus on any changes

Architecture Tests

• (Status)
• What's next:  

ABI Extensions

• None required

GCC and Assembler

• (Intrinsics)

(links to GitHub, etc., as relevant to each of the topics here)

...

• )

LLVM

SAIL

Spike

QMU

Proof-of-Concept

• RV32
  • (project name/link)
  • (extensions verified)
  • level of verification achieved (behavioral RTL/simulation, synthesized RTL/area-&-timing, actual silicon, etc.)
• RV64