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Status at a glance:

• Current  Definition-of-Done (wiki.riscv.org -> tech -> policies -> approved)   Status: kickoff  DoD status directory
• Next  update DoD checklist Plan tab, decide on any waivers needed?  Send to Chairs info below to transition from Kickoff to Plan  

To Reach Definition-of-Done Plan status: extension lifecycle and milestone definitions

• [RVS-1017] Fast Interrupts (CLIC) - RISC-V Jira (riscv.org) 
  
  • CLIC ratification status is now tracked using Jira which includes links to google docs ratification plan and status checklist
• Copy  Non-ISA Platform Ratification Template 
• keep specification status spreadsheet up-to-date ( projected dates, DoD component effort sizing, DoD tasks your group needs resource help with,...)
• Keep dashboard  Non-ISA Extensions On Deck for Freeze Milestone up-to-date
• Develop final charter and plan with the group and send to Chairs (tech-chairs@lists.riscv.org) for approval within 4 weeks
• Fill in DoD Plan tab in checklist and send to chairs for approval of any deliverables that don't match the defaults along with any requested waivers
• Freeze-time preliminary POC definition approved by IC
• Develop Rationale document and send to chairs for approval
• Notify TSC and Chairs when you complete this milestone and include any waivers and an updated DoD spreadsheet.
• Plan: RISCV has prioritized RVA22.  expect CLIC to possibly be ratified with RVM23 with other embedded extensions like Zfinx, new compressed, rv32e, p-extension.  So CLIC still on roadmap but probably next gen RISC-V grouping.  Continue working on issues and refining spec.
• Hypervisor support?
  • See issue #92 discussion.  Lastest discussion: The AIA spec is being developed to be the standard support for interrupts for standard hypervisors. Possible hypervisor directions for fast interrupts for embedded include: 1) a minimal CLIC extension that adds HS mode as another privilege layer in the stack, so the hypervisor could optionally receive interrupts and optionally enable/hide interrupts from lower privilege modes. This would allow the 2-stage translation and other features of the hypervisor to be used in a CLIC-based system, but would not support sending interrupts directly to descheduled guest OS contexts (have to route via hypervisor interrupt). 2) support multiple descheduled CLIC contexts to which interrupts could be sent directly while they were sleeping, which would be a much bigger project. 3) add an extension to AIA (instead of working on CLIC) to somehow reduce interrupt latency using the standard hypervisor stack.
• Impact of N-extension on CLIC?  Update CLIC spec to not rely on N-extension but add commentary on if N-extension is ratified how it would work with CLIC
  • .

Charter

• Current Charter at https://github.com/riscv/groups/tree/main/Fast-Interrupts 
• Calendar: https://calendar.google.com/calendar/u/0/embed?src=tech.meetings@riscv.org
• Develop a low-latency, vectored, priority-based, preemptive interrupt scheme for interrupts directed to a single hart, compatible with the existing RISC-V standards. Provide both hardware specifications and software ABIs/APIs. Standardize compiler conventions for annotating interrupt handler functions.
• Meetings Disclaimers Video

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• Latest Draft Fast Interrupt Specification (v0.9-draft-2023041120240314)

• What's next:

  • 28 0 outstanding pre-ratification issues.
    • 12 active spec issues.
      • big items: hypervisor, cliccfg reformat proposal
    • 6 issues to track Definition of Done tasks
    • 6 issues kept open for future enhancements (post rev1.0) 
    • Freeze Checklist Completed

  • Major items on Freeze Checklist: 

    • RISC-V SAIL 

    Saravana introduction.  will be working on interrupts and SAIL.  From networking background.  Coming up to speed on SAIL model.  Went through cookbook model.  Starting with PLIC.  PLIC is non-ISA.  interrupt registers  PLIC is almost completely MMIO addresses.  wires from PLIC into interrupt registers.  That I/f is sort of architectural.  hook up pseudo event generator to wiggle the wires.  if hook up PLIC have to connect to PLIC. 

    From a hart perspective there are a lot of interrupt wires coming in.  how do they get there.  incoming write addr turns into wiggling a wire.   

    Event generator relative to retired count of a hart. Assert the wire 5 instruction retires from now. As independent from implementation as possible.  instruction retires are relatively deterministic. 

    SAIL status – 1 more pull request for vector.  do have backlog.  7 or 8 prs that are pending.  some PRs may affect the same file.  instruction extension usually just a separate file.  CLIC will add CSRs and is more complicated (touch at least 3 files).  RNMI.  PRs priority things that are ratified. 

    SAIL Implementation Completed 

    • RISC-V Tests 

    If there is a PR for ACT should have been tested and compared to Spike.  riscv-non-isa/riscv-arch-test (github.com) 

    Ovpsim may be a good alternative to spike with initial development while spike is being updated.  have to do in environment that generates interrupts. 

    Regression testing – interaction with CLINT. 

    Would CLIC get its own folder under riscv-arch-test/riscv-test-suite/rv32i? 

    In one place but say execute if RV32I or RV64I or don’t run test. 

    Test plan – need to write something that stimulates clic sources, turns into wires.   

    ACT – read/understood/implemented the spec.  not DV coverage (lots of combinations).  but do want some cross-coverage.  

    ACT tests created.  Missing SHV tests.

    • RISC-V Tests Input 

    riscv-software-src/riscv-config: RISC-V Configuration Validator (github.com) 

    Schema_isa.yaml - gives allowed configuration on risc-v and allowed values.  WARL fields give allowed ranges.  10k lines in file. 

    Examples/rivc32i_isa.yaml is compared against schema_isa.yaml to see if it is allowed. 

    When add new CSRs, add PR to add to schema_isa.yaml and then will be checked against example implementation. 

    Schemas/schema_platforml.yaml - memory mapped registers (like clicintctl, etc.) 

    Run python scripts that look at your implementation and see if it is valid.  e.g., if have d then have f- extenstion, etc. checks if WARL field is valid. 

    Write anything, read legal.  mapping from what is illegal to what is legal.  mapping is arbitrary.  so prefer (easiest) if implementers implement when write something illegal, don’t write.  that works easiest for describing in this file. 

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Though all listed under "simulators", these are actually a collection of formal model / virtual machine / architectural simulators / DV simulators etc.

SAIL

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• which github? https://github.com/riscv/sail-riscv is now is the official location

Spike

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Software

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