RISC-V International
Page History
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| Project Name | Base Architecture | Level of implementation | Notes |
|---|---|---|---|
| area-optimized core | RV32/64 | RTL simulation, FPGA Implementation, Synthesis | closed / commercial source https://www.seagate.com/innovation/risc-v/ |
| high-performance core | RV32 | RTL simulation, FPGA Implementation, Synthesis | closed / commercial source https://www.seagate.com/innovation/risc-v/ |
...
| Project/Maintainer | Description |
|---|---|
ABI Extensions
- Regular C function that save/restores all caller-save registers
- Inline handler gcc interrupt attribute to always callee-save every register (save as you go)
- EABI Task Group - improve interrupt latency by reducing the number of caller-save registersTBD
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